sce 0110 - elementos de lógica digital i -...
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SCE 0110 - Elementos de Lógica Digital I
Representação Numérica e Circuitos Aritméticos
Prof. Dr. Vanderlei Bonato
Figure 5.31. Multiplication of unsigned numbers.
× 1 1 1 0
1 1 1 0 1 0 1 1
1 1 1 0 0 0 0 0
1 1 1 0 1 0 0 1 1 0 1 0
Multiplicand M Multiplier Q
Product P
(14) (11)
(154)
× 1 1 1 0
1 1 1 0 1 0 1 1
1 1 1 0
1 0 0 1 1 0 1 0
Multiplicand M Multiplier Q
Product P
(11) (14)
(154)
+ 1 0 1 0 1 0 0 0 0 +
0 1 0 1 0 1 1 1 0 +
Partial product 0
Partial product 1
Partial product 2
(a) Multiplication by hand
(b) Multiplication for implementation in hardware
“uma abordagem sequencial simples precisaria de um somador de 8 bits”
“multiplicação utilizando vários somadores, nesse caso somadores de 4bits”
Figure 5.32. A 4 x 4 multiplier ciuciut.
0
0
0
p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0
q 2
q 1
q 3
q 0
m 3 m 2 m 1 m 0 0
PP1
PP2
(a) Structure of the circuit
m k
q j
c in
Bit of PPi
FAc out
(c) A block in the bottom two rows
m k
q 1
c inFAc out
(b) A block in the top row
q 0
m k 1 +
Figure 5.33. Multiplication of signed numbers.
0 0 0 1 1 1 0 0 1 1 1 0 0 1 0 1 1
0 0 1 1 1 0 0 0 1 0 1 0 1 0 0 0 0 0 0
Multiplicand M Multiplier Q
Product P
(+14) (+11)
(+154)
+ +
0 0 0 1 0 1 0 0 0 1 1 1 0 +
0 0 1 0 0 1 1 0 0 0 0 0 0 + 0 0 1 0 0 1 1 0 1 0
Partial product 0 Partial product 1 Partial product 2 Partial product 3
× 1 1 1 0 0 1 0
1 0 0 1 0 0 1 0 1 1
1 1 0 0 1 0 1 1 0 1 0 1 1 0 0 0 0 0 0
Multiplicand M Multiplier Q
Product P
( 14) (+11)
( 154)
+ +
1 1 1 0 1 0 1 1 1 0 0 1 0 +
1 1 0 1 1 0 0 0 0 0 0 0 0 + 1 1 0 1 1 0 0 1 1 0
Partial product 0 Partial product 1 Partial product 2 Partial product 3
–
–
(a) Positive multiplicand
(b) Negative multiplicand
x
Extensão de sinal
Fixed-Point Numbers • Consist of an integer and fraction parts • Can be written in the positional number
representation B = bn-1bn-2...b1b0.b-1b-2...b-k
The value of the number is: V(B) = Σ bi x 2i
• The radix point is considered to be fixed • Logic circuits that deal with fixed-point are
essentially the same as those used for integers
n-1
i=-k
Figure 5.41. Conversion of fractions from decimal to binary.
Figure 5.42. Conversion of fixed point numbers from decimal to binary.
Floating-Point Numbers
• Aplicações científicas – Representação de números muito pequenos ou
muito grandes • Mantissa x RExponent
• Normalização – Ex.: 5.234 x 1043
ou 6.31 x 10-28
• Padrão para números binários - IEEE754
Figure 5.34. IEEE Standard floating-point formats.
Sign
32 bits
23 bits of mantissa excess-127 exponent
8-bit
52 bits of mantissa 11-bit excess-1023 exponent
64 bits
Sign
S M
S M
(a) Single precision
(c) Double precision
E
+
E
0 denotes – 1 denotes
Table 5.3. Binary-coded decimal digits.
- Sobram 6 padrões (desperdício de hardware) - Circuitos aritméticos - mais complexos
Figure 5.35. Addition of BCD digits.
+ 1 1 0 0
0 1 1 1 0 1 0 1 +
X Y Z
+ 7 5
12 0 1 1 0 +
1 0 0 1 0 carry
+ 1 0 0 0 1
1 0 0 0 1 0 0 1 +
X Y Z
+ 8 9
17 0 1 1 0 +
1 0 1 1 1 carry
S = 2
S = 7
Valor de correção
Como somar 10 + 10 em BCD?
Figure 5.36. Block diagram for a one-digit BCD adder.
4-bit adder
Detect if
MUX
4-bit adder
sum 9 >
6 0
X Y
Z
c out
c incarry-out
Adjust
S
0
Figure 5.38. Functional simulation of the VHDL code in Figure 5.37.
Figure 5.39. Circuit for a one-digit BCD adder.
c out
Four-bit adder
Two-bit adder
s 3 s 2 s 1 s 0
z 3 z 2 z 1 z 0
x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0
c in
Código ASCII
• Usado para codificar informações que são utilizadas como texto
• Não é conveniente para representar números que serão utilizados em operações aritméticas (melhor convertê-los para binário)
• Caracteres alfanuméricos (números e letras do alfabeto), pontuação e caracteres de controle
• ASCII utiliza 7 bits, podendo o bit 8 ser utilizado como bit de paridade
Table 5.4. The seven-bit ASCII code (7 bits).
Tabela ASCII