Representação Numérica e Circuitos Aritméticos

Prof. Dr. Vanderlei Bonato

SCE 0117 - Introdução à Lógica Digital

Inteiros sem sinal

•  D = dn-1, dn-2, d1d0

•  Decimal V(D) = dn-1 x 10n-1 + dn-2

x 10n-2 + ... + d0 x 100

(8547)10= 8x103 + 5x102 + 4x101 + 7x100

•  Binário V(B) = bn-1 x 2n-1 + bn-2

x 2n-2 + ... + b0 x 20 (1101)2 = 1x23 + 1x22 + 0x21 + 1x20

Definições

•  Bit •  Nibble •  Byte •  LSB (Least-Significant Bit) •  MSB (Most-Significant Bit)

Figure 5.1. Conversion from decimal to binary.

Conversão de decimal para binário

Representação de números em qualquer base

•  K = kn-1 kn-2 ... k1 k0

•  V(k) = Σ ki x ri i=0

n-1

Table 5.1. Numbers in different systems.

Sistemas de numeração

•  Em computadores o sistema de números dominante é o binário

•  A razão para o uso do sistema octal e hexadecimal (hex) é que eles servem como uma notação simplificada para números binários – Em computadores é comum o uso de 32 ou 64

bits

Conversões (continuação)

•  Binário para Octal –  Formar grupo de 3 bits

•  Binário para Hexadecimal –  Formar grupo de 4 bits

•  Octal para Binário –  Cada dígito corresponde a 3 bits

•  Hexadecimal para Binário –  Cada dígito corresponde a 4 bits

Figure 5.2. Half-adder.

Sum s

0 1 1 0

Carry c

0 0 0 1

0 0 +

0 1 + 1 0 0 0

1 0 + 1 0

1 1 + 0 1

x y + s c

Sum Carry

(a) The four possible cases

x y

0 0 1 1

0 1 0 1

(b) Truth table

x y

s

c

HAx y

s c

(c) Circuit (d) Graphical symbol

Adição de números binários

Figure 5.3. An example of addition.

X x 4 x 3 x 2 x 1 x 0 =

Y + y 4 y 3 y 2 y 1 y 0 =

Generated carries

S s 4 s 3 s 2 s 1 s 0 =

15( ) 10

10( ) 10

25( ) 10

0 1 1 1 1

0 1 0 1 0

1 1 1 0

1 1 0 0 1

Figure 5.4. Full-adder.

0 0 0 1 0 1 1 1

c i 1 + 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

c i x i y i 00 01 11 10

0 1

x i y i c i

1 1

1 1

s i x i y i c i ⊕ ⊕ =

00 01 11 10 0 1

x i y i c i

1 1 1 1

c i 1 + x i y i x i c i y i c i + + =

c i

x i y i s i

c i 1 +

(a) Truth table (b) Karnaugh maps

(c) Circuit

0 1 1 0 1 0 0 1

s i

Figure 5.5. A decomposed implementation of the full-adder circuit.

HA HA s

c

s c

c i x i y i c i 1 +

s i

c i x i y i

c i 1 +

s i

(a) Block diagram

(b) Detailed diagram

Verifique se o comportamento está correto

Figure 5.6. An n-bit ripple-carry adder.

FA

x n – 1

c n c n 1 ”

y n 1 –

s n 1 –

FA

x 1

c 2

y 1

s 1

FA c 1

x 0 y 0

s 0

c 0

MSB position LSB position

Figure 5.7. Circuit that multiplies an eight-bit unsigned number by 3.

7 x 0 y 7 y 0

x 7 x 0 y 8 y 0 y 7 x 8

s 0 s 7 c 7

0

s 0 s 8 c 8

P 9 P 8 P 0 P 3 A = :

x 1 x 0 y 8 y 0 y 7 x 8 s 0 s 8 c 8

0 0

a 7 A :

P 9 P 8 P 0 P 3 A = :

(a) Naive approach

(b) Efficient design

a 0

a 7 A : a 0

x

Figure 5.8. Formats for representation of integers.

b n 1 – b 1 b 0

Magnitude MSB

(a) Unsigned number b n 1 – b 1 b 0

Magnitude Sign

(b) Signed number

b n 2 –

0 denotes 1 denotes

+ – MSB

Table 5.2. Interpretation of four-bit signed integers.

Figure 5.9. Examples of 1’s complement addition.

+ + 1 1 0 0

1 0 1 0 0 0 1 0

0 1 1 1

0 1 0 1 0 0 1 0

+ + 0 1 1 1

1 0 1 0 1 1 0 1

0 0 1 0

0 1 0 1 1 1 0 1

1 1

0 0 1 1

1 1

1 0 0 0

2 + ( ) 5 – ( )

3 - ( ) +

5 – ( )

7 – ( ) + 2 – ( )

5 + ( ) 2 + ( ) 7 + ( )

+

5 + ( )

3 + ( ) + 2 – ( )

Figure 5.10. Examples of 2’s complement addition.

+ + 1 1 0 1

1 0 1 1 0 0 1 0

0 1 1 1

0 1 0 1 0 0 1 0

+ + 1 0 0 1

1 0 1 1 1 1 1 0

0 0 1 1

0 1 0 1 1 1 1 0

1 1

ignore ignore

5 + ( ) 2 + ( ) 7 + ( )

+

5 + ( )

3 + ( ) + 2 – ( )

2 + ( ) 5 – ( )

3 – ( ) +

5 – ( )

7 – ( ) + 2 – ( )

Figure 5.11. Examples of 2’s complement subtraction.

– 0 1 0 1 0 0 1 0

5 + ( ) 2 + ( ) 3 + ( )

– 1

ignore

+ 0 0 1 1

0 1 0 1 1 1 1 0

– 1 0 1 1 0 0 1 0 –

1

ignore

+ 1 0 0 1

1 0 1 1 1 1 1 0

– 0 1 0 1 1 1 1 0

5 + ( )

7 + ( ) – +

0 1 1 1

0 1 0 1 0 0 1 0

5 – ( )

7 – ( ) 2 + ( )

2 – ( )

– 1 0 1 1 1 1 1 0 – +

1 1 0 1

1 0 1 1 0 0 1 0 2 – ( )

5 – ( )

3 – ( )

Figure 5.12. Graphical interpretation of four-bit 2’s complement numbers.

0000 0001

0010

0011

0100

0101

0110 0111

1000 1001 1010

1011

1100

1101

1110 1111

1 + 1 – 2 +

3 + 4 +

5 + 6 +

7 +

2 – 3 –

4 – 5 –

6 – 7 – 8 –

0

Figure 5.13. Adder/subtractor unit.

s 0 s 1 s n 1 –

x 0 x 1 x n 1 –

c n n -bit adder

y 0 y 1 y n 1 –

c 0

Add ⁄ Sub control

Figure 5.14. Examples of determination of overflow.

+ + 1 0 1 1

1 0 0 1 0 0 1 0

1 0 0 1

0 1 1 1 0 0 1 0

7 + ( ) 2 + ( ) 9 + ( )

+

+ + 0 1 1 1

1 0 0 1 1 1 1 0

0 1 0 1

0 1 1 1 1 1 1 0

7 + ( )

5 + ( ) + 2 – ( )

1 1

c 4 0 = c 3 1 =

c 4 0 = c 3 0 =

c 4 1 = c 3 1 =

c 4 1 = c 3 0 =

2 + ( ) 7 – ( )

5 – ( ) +

7 – ( )

9 – ( ) + 2 – ( )

Exercícios

•  Conversões de números –  (Brown, 2005)

•  Pgs 310-312

FIM