organização básica de computadores e linguagem de montagem · arquitetura do avr 7...

Organização Básica de computadores e linguagem de

montagem

1o Semestre de 2011

Prof. Edson Borin

Introdução ao Microcontrolador AVR

• Datasheet to ATMEL ATMEGA48/88/168• 8-Bit AVR Instruction Set

Organização da Memória no AVR

• Memória de Programa – Flash

• Memória de Dados– SRAM– EEPROM

Arquitetura do AVR

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ATmega48/88/168

4. AVR CPU Core

4.1 IntroductionThis section discusses the AVR core architecture in general. The main function of the CPU coreis to ensure correct program execution. The CPU must therefore be able to access memories,perform calculations, control peripherals, and handle interrupts.

4.2 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – withseparate memories and buses for program and data. Instructions in the program memory areexecuted with a single level pipelining. While one instruction is being executed, the next instruc-tion is pre-fetched from the program memory. This concept enables instructions to be executedin every clock cycle. The program memory is In-System Reprogrammable Flash memory.

FlashProgramMemory

InstructionRegister

InstructionDecoder

ProgramCounter

Control Lines

32 x 8GeneralPurpose

Registrers

ALU

Statusand Control

I/O Lines

EEPROM

Data Bus 8-bit

DataSRAM

Dire

ct A

ddre

ssin

g

Indi

rect

Add

ress

ing

InterruptUnit

SPIUnit

WatchdogTimer

AnalogComparator

I/O Module 2

I/O Module1

I/O Module n

• Bit 7 - I: Global Interrupt Enable: • Habilita a ocorrência de interrupções. O controle de cada interrupção é realizado por um

grupo diferente de registradores, mas se este bit estiver desabilitado, todas as interrupções estarão desabilitadas.

• Bit 6 - T: Bit Copy Storage: • Operações de cópia de bits (BLD, BST) utilizam este bit como fonte ou destino.

• Bit 5 - H: Half Carry Flag: • Indica ocorrência de Half Carry (Carry do bit 3 para o 4) em algumas operações aritméticas

( útil em aritmética BCD).• Bit 4 - S: Sign Bit:

• Sempre é um "ou exclusivo' entre o Bit 2 e Bit 3.• Bit 3 - V: Two's Complement Overow Flag:

• Indica overflow em operações aritméticas com complemento a 2.• Bit 2 - N: Negative Flag:

• Indica um resultado negativo em uma operação lógica/aritmética.• Bit 1 - Z: Zero Flag:

• Indica um resultado igual a zero em uma operação lógica/aritmética.• Bit 0 - C: Carry Flag:

• Indica ocorrência de carry em uma operação lógica/aritmética.

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4.4 Status RegisterThe Status Register contains information about the result of the most recently executed arith-metic instruction. This information can be used for altering program flow in order to performconditional operations. Note that the Status Register is updated after all ALU operations, asspecified in the Instruction Set Reference. This will in many cases remove the need for using thededicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restoredwhen returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

• Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-rupt enable control is then performed in separate control registers. If the Global Interrupt EnableRegister is cleared, none of the interrupts are enabled independent of the individual interruptenable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set bythe RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared bythe application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy StorageThe Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-nation for the operated bit. A bit from a register in the Register File can be copied into T by theBST instruction, and a bit in T can be copied into a bit in a register in the Register File by theBLD instruction.

• Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is usefulin BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N!" VThe S-bit is always an exclusive or between the Negative Flag N and the Two’s ComplementOverflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow FlagThe Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative result in an arithmetic or logic operation. See the“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero FlagThe Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “InstructionSet Description” for detailed information.

Bit 7 6 5 4 3 2 1 0

I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Registrador de estado do AVR (Status Register)

Registradores de propósito geral (32)

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• Bit 0 – C: Carry FlagThe Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction SetDescription” for detailed information.

4.5 General Purpose Register FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order to achievethe required performance and flexibility, the following input/output schemes are supported by theRegister File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, andmost of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a data memory address, mapping themdirectly into the first 32 locations of the user Data Space. Although not being physically imple-mented as SRAM locations, this memory organization provides great flexibility in access of theregisters, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

Registradores especiais: X, Y e Z

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4.5.1 The X-register, Y-register, and Z-registerThe registers R26..R31 have some added functions to their general purpose usage. These reg-isters are 16-bit address pointers for indirect addressing of the data space. The three indirectaddress registers X, Y, and Z are defined as described in Figure 4-3.

Figure 4-3. The X-, Y-, and Z-registers

In the different addressing modes these address registers have functions as fixed displacement,automatic increment, and automatic decrement (see the instruction set reference for details).

4.6 Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and for storingreturn addresses after interrupts and subroutine calls. The Stack Pointer Register always pointsto the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-tions to lower memory locations. This implies that a Stack PUSH command decreases the StackPointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and InterruptStacks are located. This Stack space in the data SRAM must be defined by the program beforeany subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set topoint above 0x0100, preferably RAMEND. The Stack Pointer is decremented by one when datais pushed onto the Stack with the PUSH instruction, and it is decremented by two when thereturn address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer isincremented by one when data is popped from the Stack with the POP instruction, and it is incre-mented by two when data is popped from the Stack with return from subroutine RET or returnfrom interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number ofbits actually used is implementation dependent. Note that the data space in some implementa-tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Registerwill not be present.

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

Bit 15 14 13 12 11 10 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

7 6 5 4 3 2 1 0


R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

• R26 a R31 podem ser utilizados em pares como registradores de 16 bits: • Ex: X = R27:R26

Registrador de Pilha: Stack Pointer

• Pilha é usada para armazenamento de dados temporários• Registrador SP aponta para o topo da pilha.• Pilha “cresce” de endereços maiores para menores.

• PUSH na pulha decrementa SP.• Usuário deve inicializar o SP.

• Tem que ser acima do endereço 0x100h, de preferência no endereço RAMEND (Endereço mais alto da memória)

Memória de Programa do AVR ATmega88/168

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Figure 5-1. Program Memory Map, ATmega48

Figure 5-2. Program Memory Map, ATmega88 and ATmega168

0x0000

0x7FF

Program Memory

Application Flash Section

0x0000

0x0FFF/0x1FFF

Program Memory

Application Flash Section

Boot Flash Section

MemóriaFlash

Memória de Dados do AVR ATmega88/168

MemóriaSRAM

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5.2 SRAM Data MemoryFigure 5-3 shows how the ATmega48/88/168 SRAM Memory is organized.

The ATmega48/88/168 is a complex microcontroller with more peripheral units than can be sup-ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For theExtended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instruc-tions can be used.

The lower 768/1280/1280 data memory locations address both the Register File, the I/O mem-ory, Extended I/O memory, and the internal data SRAM. The first 32 locations address theRegister File, the next 64 location the standard I/O memory, then 160 locations of Extended I/Omemory, and the next 512/1024/1024 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the RegisterFile, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address givenby the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, andthe 512/1024/1024 bytes of internal data SRAM in the ATmega48/88/168 are all accessiblethrough all these addressing modes. The Register File is described in ”General Purpose Regis-ter File” on page 10.

Figure 5-3. Data Memory Map

5.2.1 Data Memory Access TimesThis section describes the general access timing concepts for internal memory access. Theinternal data SRAM access is performed in two clkCPU cycles as described in Figure 5-4.

32 Registers64 I/O Registers

Internal SRAM(512/1024/1024 x 8)

0x0000 - 0x001F0x0020 - 0x005F

0x02FF/0x04FF/0x04FF

0x0060 - 0x00FF

Data Memory

160 Ext I/O Reg.0x0100


Memória EEPROM (512 bytes)

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ATmega48/88/168

5.3.2 The EEPROM Address Register – EEARH and EEARL

• Bits 15..9 – Res: Reserved BitsThese bits are reserved bits in the ATmega48/88/168 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM AddressThe EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the256/512/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0and 255/511/511. The initial value of EEAR is undefined. A proper value must be written beforethe EEPROM may be accessed.

EEAR8 is an unused bit in ATmega48 and must always be written to zero.

5.3.3 The EEPROM Data Register – EEDR

• Bits 7..0 – EEDR7.0: EEPROM DataFor the EEPROM write operation, the EEDR Register contains the data to be written to theEEPROM in the address given by the EEAR Register. For the EEPROM read operation, theEEDR contains the data read out from the EEPROM at the address given by EEAR.

5.3.4 The EEPROM Control Register – EECR


• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode BitsThe EEPROM Programming mode bit setting defines which programming action that will be trig-gered when writing EEPE. It is possible to program data in one atomic operation (erase the oldvalue and program the new value) or to split the Erase and Write operations in two differentoperations. The Programming times for the different modes are shown in Table 5-1. While EEPE

Bit 15 14 13 12 11 10 9 8

– – – – – – – EEAR8 EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

7 6 5 4 3 2 1 0

Read/Write R R R R R R R R/W


Initial Value 0 0 0 0 0 0 0 X

X X X X X X X X

Bit 7 6 5 4 3 2 1 0

MSB LSB EEDR



Bit 7 6 5 4 3 2 1 0

– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X 0 0 X 0

192545E–AVR–02/05

ATmega48/88/168










Bit 15 14 13 12 11 10 9 8

– – – – – – – EEAR8 EEARH


7 6 5 4 3 2 1 0




X X X X X X X X

Bit 7 6 5 4 3 2 1 0

MSB LSB EEDR



Bit 7 6 5 4 3 2 1 0





192545E–AVR–02/05

ATmega48/88/168










Bit 15 14 13 12 11 10 9 8

– – – – – – – EEAR8 EEARH


7 6 5 4 3 2 1 0




X X X X X X X X

Bit 7 6 5 4 3 2 1 0

MSB LSB EEDR



Bit 7 6 5 4 3 2 1 0




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ATmega48/88/168

is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00unless the EEPROM is busy programming.

• Bit 3 – EERIE: EEPROM Ready Interrupt EnableWriting EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. WritingEERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-rupt when EEPE is cleared. The interrupt will not be generated during EEPROM write or SPM.

• Bit 2 – EEMPE: EEPROM Master Write EnableThe EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at theselected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has beenwritten to one by software, hardware clears the bit to zero after four clock cycles. See thedescription of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Write EnableThe EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When addressand data are correctly set up, the EEPE bit must be written to one to write the value into theEEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, other-wise no EEPROM write takes place. The following procedure should be followed when writingthe EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.2. Wait until SELFPRGEN in SPMCSR becomes zero.3. Write new EEPROM address to EEAR (optional).4. Write new EEPROM data to EEDR (optional).5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.The EEPROM can not be programmed during a CPU write to the Flash memory. The softwaremust check that the Flash programming is completed before initiating a new EEPROM write.Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program theFlash. If the Flash is never being updated by the CPU, step 2 can be omitted. See ”Boot LoaderSupport – Read-While-Write Self-Programming, ATmega88 and ATmega168” on page 264 fordetails about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since theEEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM isinterrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing theinterrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag clearedduring all the steps to avoid these problems.

Table 5-1. EEPROM Mode Bits

EEPM1 EEPM0Programming

Time Operation

0 0 3.4 ms Erase and Write in one operation (Atomic Operation)

0 1 1.8 ms Erase Only

1 0 1.8 ms Write Only

1 1 – Reserved for future use

Memória EEPROM (512 bytes)

• Endereçamento da memória de dados (SRAM, Registradores, E/S e E/S extendido)– Acesso direto a um registrador de propósito geral– Acesso direto a 2 registradores de propósito geral– Acesso direto à registradores de E/S– Acesso direto à memória de dados– Acesso indireto à memória de dados– Acesso indireto à memória de dados com deslocamento– Acesso indireto à memória de dados com pré-decremento– Acesso indireto à memória de dados com pós-incremento

Modos de endereçamento do AVR

Acesso direto a um registrador de propósito geral

3

AVR Instruction Set

0856D–AVR–08/02

The Program and Data Addressing Modes

The AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the Programmemory (Flash) and Data memory (SRAM, Register file, I/O Memory, and Extended I/O Memory). This section describesthe various addressing modes supported by the AVR architecture. In the following figures, OP means the operation codepart of the instruction word. To simplify, not all figures show the exact location of the addressing bits. To generalize, theabstract terms RAMEND and FLASHEND have been used to represent the highest location in data and program space,respectively.Note: Not all addressing modes are present in all devices. Refer to the device spesific instruction summary.

Register Direct, Single Register Rd

Figure 1. Direct Single Register Addressing

The operand is contained in register d (Rd).

Register Direct, Two Registers Rd and Rr

Figure 2. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

Acesso direto a 2 registradores de propósito geral

3

AVR Instruction Set

0856D–AVR–08/02

The Program and Data Addressing Modes

The AVR Enhanced RISC microcontroller supports powerful and efficient addressing modes for access to the Programmemory (Flash) and Data memory (SRAM, Register file, I/O Memory, and Extended I/O Memory). This section describesthe various addressing modes supported by the AVR architecture. In the following figures, OP means the operation codepart of the instruction word. To simplify, not all figures show the exact location of the addressing bits. To generalize, theabstract terms RAMEND and FLASHEND have been used to represent the highest location in data and program space,respectively.Note: Not all addressing modes are present in all devices. Refer to the device spesific instruction summary.

Register Direct, Single Register Rd

Figure 1. Direct Single Register Addressing

The operand is contained in register d (Rd).

Register Direct, Two Registers Rd and Rr

Figure 2. Direct Register Addressing, Two Registers

Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd).

Acesso direto à registradores de E/S

4 AVR Instruction Set0856D–AVR–08/02

I/O Direct

Figure 3. I/O Direct Addressing

Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.Note: Some complex AVR Microcontrollers have more peripheral units than can be supported within the 64 locations reserved in the

opcode for I/O direct addressing. The extended I/O memory from address 64 to 255 can only be reached by data addressing,not I/O addressing.

Data Direct

Figure 4. Direct Data Addressing

A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or sourceregister.

OP Rr/Rd1631

15 0Data Address

0x0000

RAMEND

20 19Data Space

Acesso direto à memória de dados


I/O Direct

Figure 3. I/O Direct Addressing

Operand address is contained in 6 bits of the instruction word. n is the destination or source register address.Note: Some complex AVR Microcontrollers have more peripheral units than can be supported within the 64 locations reserved in the

opcode for I/O direct addressing. The extended I/O memory from address 64 to 255 can only be reached by data addressing,not I/O addressing.

Data Direct

Figure 4. Direct Data Addressing

A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr specify the destination or sourceregister.

OP Rr/Rd1631

15 0Data Address

0x0000

RAMEND

20 19Data Space

Acesso indireto à memória de dados

5

AVR Instruction Set

0856D–AVR–08/02

Data Indirect with Displacement

Figure 5. Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instructionword. Rd/Rr specify the destination or source register.

Data Indirect

Figure 6. Data Indirect Addressing

Operand address is the contents of the X-, Y-, or the Z-register. In AVR devices without SRAM, Data Indirect Addressing iscalled Register Indirect Addressing. Register Indirect Addressing is a subset of Data Indirect Addressing since the dataspace form 0 to 31 is the Register File.

Data Space0x0000

RAMEND

Y OR Z - REGISTER

OP qRr/Rd

0

05610

15

15

Data Space0x0000

X, Y OR Z - REGISTER

015

RAMEND

Acesso indireto à memória de dados com deslocamento

5

AVR Instruction Set

0856D–AVR–08/02

Data Indirect with Displacement

Figure 5. Data Indirect with Displacement

Operand address is the result of the Y- or Z-register contents added to the address contained in 6 bits of the instructionword. Rd/Rr specify the destination or source register.

Data Indirect

Figure 6. Data Indirect Addressing

Operand address is the contents of the X-, Y-, or the Z-register. In AVR devices without SRAM, Data Indirect Addressing iscalled Register Indirect Addressing. Register Indirect Addressing is a subset of Data Indirect Addressing since the dataspace form 0 to 31 is the Register File.

Data Space0x0000

RAMEND

Y OR Z - REGISTER

OP qRr/Rd

0

05610

15

15

Data Space0x0000


015

RAMEND

Acesso indireto à memória de dados com pré-decremento


Data Indirect with Pre-decrement

Figure 7. Data Indirect Addressing with Pre-decrement

The X,- Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-,Y-, or the Z-register.

Data Indirect with Post-increment

Figure 8. Data Indirect Addressing with Post-increment

The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-regis-ter prior to incrementing.

Data Space0x0000


015

-1

RAMEND

Data Space0x0000


015

1

RAMEND

Acesso indireto à memória de dados com pós-incremento


Data Indirect with Pre-decrement

Figure 7. Data Indirect Addressing with Pre-decrement

The X,- Y-, or the Z-register is decremented before the operation. Operand address is the decremented contents of the X-,Y-, or the Z-register.

Data Indirect with Post-increment

Figure 8. Data Indirect Addressing with Post-increment

The X-, Y-, or the Z-register is incremented after the operation. Operand address is the content of the X-, Y-, or the Z-regis-ter prior to incrementing.

Data Space0x0000


015

-1

RAMEND

Data Space0x0000


015

1

RAMEND

• Endereçamento da memória de programa (Flash)– Leitura/Escrita na memória de programa– Leitura da memória de programa com pós-incremento– Desvio de fluxo de controle direto– Desvio de fluxo de controle indireto– Desvio de fluxo de controle relativo–

Modos de endereçamento do AVR

Leitura/Escrita na memória de programa

7

AVR Instruction Set

0856D–AVR–08/02

Program Memory Constant Addressing using the LPM, ELPM, and SPM Instructions

Figure 9. Program Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. For LPM, the LSB selectslow byte if cleared (LSB = 0) or high byte if set (LSB = 1). For SPM, the LSB should be cleared. If ELPM is used, theRAMPZ Register is used to extend the Z-register.

Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction

Figure 10. Program Memory Addressing with Post-increment

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. The LSB selects low byteif cleared (LSB = 0) or high byte if set (LSB = 1). If ELPM Z+ is used, the RAMPZ Register is used to extend the Z-register.

FLASHEND

0x0000

LSB

FLASHEND

0x0000

1

LSB

Instruções: LPM, ELPM e SPM

Leitura da memória de programa com pós-incremento

Instruções: LPM Z+ e ELPM Z+ (Pós-incremento)

7

AVR Instruction Set

0856D–AVR–08/02

Program Memory Constant Addressing using the LPM, ELPM, and SPM Instructions

Figure 9. Program Memory Constant Addressing

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. For LPM, the LSB selectslow byte if cleared (LSB = 0) or high byte if set (LSB = 1). For SPM, the LSB should be cleared. If ELPM is used, theRAMPZ Register is used to extend the Z-register.

Program Memory with Post-increment using the LPM Z+ and ELPM Z+ Instruction

Figure 10. Program Memory Addressing with Post-increment

Constant byte address is specified by the Z-register contents. The 15 MSBs select word address. The LSB selects low byteif cleared (LSB = 0) or high byte if set (LSB = 1). If ELPM Z+ is used, the RAMPZ Register is used to extend the Z-register.

FLASHEND

0x0000

LSB

FLASHEND

0x0000

1

LSB

Desvio de fluxo de controle direto

Instruções: JMP e CALL


Direct Program Addressing, JMP and CALL

Figure 11. Direct Program Memory Addressing

Program execution continues at the address immediate in the instruction word.

Indirect Program Addressing, IJMP and ICALL

Figure 12. Indirect Program Memory Addressing

Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).

FLASHEND

31 16OP 6 MSB

16 LSB

PC21 0

15 0

0x0000

FLASHEND

PC15 0

0x0000

Desvio de fluxo de controle indireto

Instruções: IJMP e ICALL


Direct Program Addressing, JMP and CALL

Figure 11. Direct Program Memory Addressing

Program execution continues at the address immediate in the instruction word.

Indirect Program Addressing, IJMP and ICALL

Figure 12. Indirect Program Memory Addressing

Program execution continues at address contained by the Z-register (i.e., the PC is loaded with the contents of the Z-register).

FLASHEND

31 16OP 6 MSB

16 LSB

PC21 0

15 0

0x0000

FLASHEND

PC15 0

0x0000

Desvio de fluxo de controle relativo

Instruções: RJMP e RCALL

9

AVR Instruction Set

0856D–AVR–08/02

Relative Program Addressing, RJMP and RCALL

Figure 13. Relative Program Memory Addressing

Program execution continues at address PC + k + 1. The relative address k is from -2048 to 2047.

FLASHEND

1

0x0000

Resumo do conjunto de instruções

11

AVR Instruction Set

0856D–AVR–08/02

Complete Instruction Set Summary

Instruction Set Summary

Mnemonics Operands Description Operation Flags#ClockNote

Arithmetic and Logic Instructions

ADD Rd, Rr Add without Carry Rd! Rd + Rr Z,C,N,V,S,H 1

ADC Rd, Rr Add with Carry Rd! Rd + Rr + C Z,C,N,V,S,H 1

ADIW Rd, K Add Immediate to Word Rd+1:Rd! Rd+1:Rd + K Z,C,N,V,S 2 (1)

SUB Rd, Rr Subtract without Carry Rd! Rd - Rr Z,C,N,V,S,H 1

SUBI Rd, K Subtract Immediate Rd! Rd - K Z,C,N,V,S,H 1

SBC Rd, Rr Subtract with Carry Rd! Rd - Rr - C Z,C,N,V,S,H 1

SBCI Rd, K Subtract Immediate with Carry Rd! Rd - K - C Z,C,N,V,S,H 1

SBIW Rd, K Subtract Immediate from Word Rd+1:Rd! Rd+1:Rd - K Z,C,N,V,S 2 (1)

AND Rd, Rr Logical AND Rd! Rd • Rr Z,N,V,S 1

ANDI Rd, K Logical AND with Immediate Rd! Rd • K Z,N,V,S 1

OR Rd, Rr Logical OR Rd! Rd v Rr Z,N,V,S 1

ORI Rd, K Logical OR with Immediate Rd! Rd v K Z,N,V,S 1

EOR Rd, Rr Exclusive OR Rd! Rd " Rr Z,N,V,S 1

COM Rd One’s Complement Rd! $FF - Rd Z,C,N,V,S 1

NEG Rd Two’s Complement Rd! $00 - Rd Z,C,N,V,S,H 1

SBR Rd,K Set Bit(s) in Register Rd! Rd v K Z,N,V,S 1

CBR Rd,K Clear Bit(s) in Register Rd! Rd • ($FFh - K) Z,N,V,S 1

INC Rd Increment Rd! Rd + 1 Z,N,V,S 1

DEC Rd Decrement Rd! Rd - 1 Z,N,V,S 1

TST Rd Test for Zero or Minus Rd! Rd • Rd Z,N,V,S 1

CLR Rd Clear Register Rd ! Rd " Rd Z,N,V,S 1

SER Rd Set Register Rd! $FF None 1

MUL Rd,Rr Multiply Unsigned R1:R0! Rd # Rr (UU) Z,C 2 (1)

MULS Rd,Rr Multiply Signed R1:R0! Rd # Rr (SS) Z,C 2 (1)

MULSU Rd,Rr Multiply Signed with Unsigned R1:R0! Rd # Rr (SU) Z,C 2 (1)

FMUL Rd,Rr Fractional Multiply Unsigned R1:R0! (Rd # Rr)<<1 (UU) Z,C 2 (1)

FMULS Rd,Rr Fractional Multiply Signed R1:R0! (Rd # Rr)<<1 (SS) Z,C 2 (1)

FMULSU Rd,Rr Fractional Multiply Signed withUnsigned

R1:R0! (Rd # Rr)<<1 (SU) Z,C 2 (1)

Branch Instructions

RJMP k Relative Jump PC! PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC(15:0)! Z, PC(21:16)! 0 None 2 (1)

11

AVR Instruction Set

0856D–AVR–08/02

































R1:R0! (Rd # Rr)<<1 (SU) Z,C 2 (1)

Branch Instructions




11

AVR Instruction Set

0856D–AVR–08/02

































R1:R0! (Rd # Rr)<<1 (SU) Z,C 2 (1)

Branch Instructions



11

AVR Instruction Set

0856D–AVR–08/02

































R1:R0! (Rd # Rr)<<1 (SU) Z,C 2 (1)

Branch Instructions




EIJMP Extended Indirect Jump to (Z) PC(15:0)! Z, PC(21:16)! EIND None 2 (1)

JMP k Jump PC! k None 3 (1)

RCALL k Relative Call Subroutine PC! PC + k + 1 None 3 / 4 (4)

ICALL Indirect Call to (Z) PC(15:0)! Z, PC(21:16)! 0 None 3 / 4 (1)(4)

EICALL Extended Indirect Call to (Z) PC(15:0)! Z, PC(21:16)! EIND None 4 (1)(4)

CALL k Call Subroutine PC! k None 4 / 5 (1)(4)

RET Subroutine Return PC! STACK None 4 / 5 (4)

RETI Interrupt Return PC! STACK I 4 / 5 (4)

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ! PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1

CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1

CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ! PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register Set if (Rr(b)=1) PC ! PC + 2 or 3 None 1 / 2 / 3

SBIC A, b Skip if Bit in I/O Register Cleared if(I/O(A,b)=0) PC ! PC + 2 or 3 None 1 / 2 / 3

SBIS A, b Skip if Bit in I/O Register Set If(I/O(A,b)=1) PC! PC + 2 or 3 None 1 / 2 / 3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC!PC+k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC!PC+k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC! PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC! PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC ! PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC ! PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC ! PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC ! PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC ! PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC ! PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N " V= 0) then PC! PC + k + 1 None 1 / 2

BRLT k Branch if Less Than, Signed if (N " V= 1) then PC! PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ! PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ! PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC! PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC! PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC! PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC! PC + k + 1 None 1 / 2

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC! PC + k + 1 None 1 / 2

Instruction Set Summary (Continued)



11

AVR Instruction Set

0856D–AVR–08/02

































R1:R0! (Rd # Rr)<<1 (SU) Z,C 2 (1)

Branch Instructions




EIJMP Extended Indirect Jump to (Z) PC(15:0)! Z, PC(21:16)! EIND None 2 (1)

JMP k Jump PC! k None 3 (1)

RCALL k Relative Call Subroutine PC! PC + k + 1 None 3 / 4 (4)

ICALL Indirect Call to (Z) PC(15:0)! Z, PC(21:16)! 0 None 3 / 4 (1)(4)

EICALL Extended Indirect Call to (Z) PC(15:0)! Z, PC(21:16)! EIND None 4 (1)(4)

CALL k Call Subroutine PC! k None 4 / 5 (1)(4)

RET Subroutine Return PC! STACK None 4 / 5 (4)

RETI Interrupt Return PC! STACK I 4 / 5 (4)

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ! PC + 2 or 3 None 1 / 2 / 3

CP Rd,Rr Compare Rd - Rr Z,C,N,V,S,H 1

CPC Rd,Rr Compare with Carry Rd - Rr - C Z,C,N,V,S,H 1

CPI Rd,K Compare with Immediate Rd - K Z,C,N,V,S,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ! PC + 2 or 3 None 1 / 2 / 3

SBRS Rr, b Skip if Bit in Register Set if (Rr(b)=1) PC ! PC + 2 or 3 None 1 / 2 / 3

SBIC A, b Skip if Bit in I/O Register Cleared if(I/O(A,b)=0) PC ! PC + 2 or 3 None 1 / 2 / 3

SBIS A, b Skip if Bit in I/O Register Set If(I/O(A,b)=1) PC! PC + 2 or 3 None 1 / 2 / 3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC!PC+k + 1 None 1 / 2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC!PC+k + 1 None 1 / 2

BREQ k Branch if Equal if (Z = 1) then PC! PC + k + 1 None 1 / 2

BRNE k Branch if Not Equal if (Z = 0) then PC! PC + k + 1 None 1 / 2

BRCS k Branch if Carry Set if (C = 1) then PC ! PC + k + 1 None 1 / 2

BRCC k Branch if Carry Cleared if (C = 0) then PC ! PC + k + 1 None 1 / 2

BRSH k Branch if Same or Higher if (C = 0) then PC ! PC + k + 1 None 1 / 2

BRLO k Branch if Lower if (C = 1) then PC ! PC + k + 1 None 1 / 2

BRMI k Branch if Minus if (N = 1) then PC ! PC + k + 1 None 1 / 2

BRPL k Branch if Plus if (N = 0) then PC ! PC + k + 1 None 1 / 2

BRGE k Branch if Greater or Equal, Signed if (N " V= 0) then PC! PC + k + 1 None 1 / 2

BRLT k Branch if Less Than, Signed if (N " V= 1) then PC! PC + k + 1 None 1 / 2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ! PC + k + 1 None 1 / 2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ! PC + k + 1 None 1 / 2

BRTS k Branch if T Flag Set if (T = 1) then PC! PC + k + 1 None 1 / 2

BRTC k Branch if T Flag Cleared if (T = 0) then PC! PC + k + 1 None 1 / 2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC! PC + k + 1 None 1 / 2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC! PC + k + 1 None 1 / 2

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC! PC + k + 1 None 1 / 2

Instruction Set Summary (Continued)


Desvio condicional

Instruções: BRLT, BRGE, BRSH, ...


Conditional Branch Summary

Note: 1. Interchange Rd and Rr in the operation before the test, i.e., CP Rd,Rr! CP Rr,Rd

Test Boolean Mnemonic Complementary Boolean Mnemonic Comment

Rd > Rr Z•(N " V) = 0 BRLT(1) Rd # Rr Z+(N " V) = 1 BRGE* SignedRd $ Rr (N " V) = 0 BRGE Rd < Rr (N " V) = 1 BRLT SignedRd = Rr Z = 1 BREQ Rd % Rr Z = 0 BRNE SignedRd # Rr Z+(N " V) = 1 BRGE(1) Rd > Rr Z•(N " V) = 0 BRLT* SignedRd < Rr (N " V) = 1 BRLT Rd $ Rr (N " V) = 0 BRGE SignedRd > Rr C + Z = 0 BRLO(1) Rd # Rr C + Z = 1 BRSH* UnsignedRd $ Rr C = 0 BRSH/BRCC Rd < Rr C = 1 BRLO/BRCS UnsignedRd = Rr Z = 1 BREQ Rd % Rr Z = 0 BRNE UnsignedRd # Rr C + Z = 1 BRSH(1) Rd > Rr C + Z = 0 BRLO* UnsignedRd < Rr C = 1 BRLO/BRCS Rd $ Rr C = 0 BRSH/BRCC UnsignedCarry C = 1 BRCS No carry C = 0 BRCC SimpleNegative N = 1 BRMI Positive N = 0 BRPL SimpleOverflow V = 1 BRVS No overflow V = 0 BRVC SimpleZero Z = 1 BREQ Not zero Z = 0 BRNE Simple

Example:adiw r25:24,1 ; Add 1 to r25:r24adiw ZH:ZL,63 ; Add 63 to the Z-pointer(r31:r30)

Example:ldi r16,$10 ; Load decimal 16 into r16asr r16 ; r16=r16 / 2ldi r17,$FC ; Load -4 in r17asr r17 ; r17=r17/2

Example:add r0,r4 ; Add r4 to r0lsr r0 ; Divide r0 by 2

Example:add r0,r4 ; Add r4 to r0lsl r0 ; Multiply r0 by 2

Example:lsl r18 ; Multiply r19:r18 by tworol r19 ; r19:r18 is a signed or unsigned two-byte integer

Example:lsr r19 ; Divide r19:r18 by tworor r18 ; r19:r18 is an unsigned two-byte integer

Example:clr r27 ; Clear X high byteldi r26,$60 ; Set X low byte to $60ld r0,X+ ; Load r0 with data space loc. $60(X post inc)ld r1,X ; Load r1 with data space loc. $61ldi r26,$63 ; Set X low byte to $63ld r2,X ; Load r2 with data space loc. $63ld r3,–X ; Load r3 with data space loc. $62(X pre dec)

Example:

clr r27 ; Clear X high byteldi r26,$60 ; Set X low byte to $60st X+,r0 ; Store r0 in data space loc. $60(X post inc)st X,r1 ; Store r1 in data space loc. $61ldi r26,$63 ; Set X low byte to $63st X,r2 ; Store r2 in data space loc. $63st -X,r3 ; Store r3 in data space loc. $62(X pre dec)

ST – contd.

STS

Example: lds r2,$FF00 ; Load r2 with the contents of data space location $FF00 add r2,r1 ; add r1 to r2 sts $FF00,r2 ; Write back

Example:

add r22,r23 ; Add r23 to r22brcc nocarry ; Branch if carry cleared...nocarry: nop ; Branch destination (do nothing)

Example:

cpi r16,$42 ; Compare r16 to $42brne error ; Branch if r16 <> $42rjmp ok ; Unconditional brancherror: add r16,r17 ; Add r17 to r16inc r16 ; Increment r16ok: nop ; Destination for rjmp (do nothing)

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