1 flutuação de dopantes efeitos quánticos problemas variação do v th intersubband scattering

1

• Flutuação de Dopantes

•Efeitos Quánticos

ProblemasProblemas

• Variação do VTH

•Intersubband scattering

2

Electron concentration (Poisson) Electron concentration (Poisson+Schrödinger )

Wsi

tsi

Wsi=tsi=20 nm / MS=0V / VG= 0.0V / VG2=0V / Na=5x1017 cm-3 / T=300K

3

Wsi=tsi=20 nm / MS=0V / VG= 1.5V / VG2=0V / Na=5x1017 cm-3 / T=300K

Wsi

tsi


4


Wsi

tsi

Wsi=tsi= 5 nm / MS=0V / VG=0.0V / VG2=0V / Na=5x1017 cm-3 / T=300K

5


Wsi=tsi= 5 nm / MS=0V / VG=1.5V / VG2=0V / Na=5x1017 cm-3 / T=300K

Wsi

tsi

6

2D Simulation (Quantum)

Electron concentration

7



ProblemasProblemas



8

0 5 10 15 200

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

Silicon width and thickness (nm)

Ene

rgy

abo

ve E

c (eV

) o

r T

hre

shol

d v

olta

ge

(V)

First energy level at flatband (eV)First energy level at threshold (eV)Threshold voltage (V)

First (lowest) subband energy level and Threshold voltage

First (lowest) subband energy level and Threshold voltage

"Quantum-Mechanical Effects in Trigate SOI MOSFETs", J.P. Colinge, J. C. Alderman , W. Xiong, and C. R. Cleavelin, IEEE Transactions on Electron Devices, Vol. 53, no 5, pp. 1131-1136, 2006

9

-0.1 0 0.1 0.2 0.3 0.4 0.5 0.610

-12

10-11

10-10

10-9

10-8

10-7

10-6

Dra

in c

urr

ent

(A)

Gate Voltage(V)

SchrodingerPoisson

Dra

in c

urre

nt (

A)

Gate voltage (V)

W = tsi = 20 nm

10 nm

5 nm3 nm

2 nm

.. P P+S

Corrente de DrenoCorrente de DrenoPoisson equation only (P) or Poisson+Schrödinger solver (P+S)

"Quantum-Mechanical Effects in Trigate SOI MOSFETs", J.P. Colinge, J. C. Alderman , W. Xiong, and C. R. Cleavelin, IEEE Transactions on Electron Devices, Vol. 53, no 5, pp. 1131-1136, 2006

10



ProblemasProblemas



11

Inter-SubbandScattering(2D GaAs)

Inter-SubbandScattering(2D GaAs)

12

0 1 2 3 4 5

x 1020

-0.56

-0.5598

-0.5596

-0.5594

-0.5592

-0.559

-0.5588

-0.5586

-0.5584

-0.5582

-0.558

Density of States * Fermi distribution (cm-3 eV-1)

En

erg

y a

bove

Ec (

eV)

En

erg

y a

bove

Eco

(eV

)

Density of states (cm-3 eV-1)

150 eV

Silicon

Fin

Polysilicon Gate

Buried Oxide

20 nm

tsi

W

0 0.1 0.2 0.30

0.5

1

1.5

2

2.5

3

3.5

4x 10

-7

Cur

rent

(A

)

Gate Voltage (V)

DT=5K, V

S=50mV

DT=150K, V

S=0.2mV

T=28K, VDS

=0.2mV

T=8K, VDS

=0.2mV

T=4.4K, VDS

=0.2mV

(x 0.004)

Efeitos Quánticos: Inter-subband scattering

At low temperature

13

56.5 nm

11.1 nm

1.7 nm

5.7 nm

4.2 nm

0 2 4 6 8 10

x 1020

-0.775

-0.77

-0.765

-0.76

-0.755

-0.75

Density of States (cm-3 eV-1)

Ene

rgy

ab

ove

Eco

(e

V)

1 meV

5 meV

Density of states (cm-3 eV-1)

Ene

rgy

abov

e E

Co

(e

V)

At room temperature !

Efeitos Quánticos: Inter-subband scattering

USP - University of Sao Paulo

University of Sao Paulo, Brazil - Imec, Belgium

•150nm Buried oxide

•65 nm top silicon layer thickness (HFIN)

•gate dielectric = 2.3 nm HfSiON on 1 nm SiO2

•midgap metal gate:5 nm TiN layer + 100nm thick polysilicon capping

•1 x1015cm-3 channel concentration

Experimental ResultsFinFET/Tri-Gate Technology




2*

22

2 ...2

.

..

...2ln

.

finfini

OXmith WmqWnq

TkC

q

TkV

15

*T. Poiroux et al., Microelectronics Engineering, 80, 378 (2005).

For MuGFETs Devices (*):

Threshold Voltage - MuGFET

The influence of side gates areconsiderably higher than the top gate for Wfin = 20 nm (almost double gate)

Top gate

Side gate

Side gate




2*

22

2 ...2

.

..

...2ln

.

finfini

OXmith WmqWnq

TkC

q

TkV

16


For MuGFETs Devices (*):


Workfunction difference Between the gate and silicon film




2*

22

2 ...2

.

..

...2ln

.

finfini

OXmith WmqWnq

TkC

q

TkV

17

Tk

Eg

i eTn ..22

316 ..10.9,3

For MuGFETs Devices:


Potential in the channel




2*

22

2 ...2

.

..

...2ln

.

finfini

OXmith WmqWnq

TkC

q

TkV

18

Confinement inducedby the quantum wellWFIN = 20 nm




variation of the minimum energy in the conduction band




2*

22

2 ...2

.

..

...2ln

.

finfini

OXmith WmqWnq

TkC

q

TkV

19

Confinement inducedby the quantum wellWFIN = 20 nm

Therefore the last term can be neglected due to the Wfin used in this study has 20 nm





When WFin decreases

Better control of the back channel by side walls

gm ramp disappears

WFin Vth

[6] T. Poiroux et al., Micr. Eng., vol. 80, p. 378, 2005.

gmmax reduction is due to the electron mobility

degradation in sidewall (110) crystal orientation with respect to the (100) plane

WFin Sidewalls conduction



Triple-Gate nFETStrain Technology

Vth

gm,max

Strain



NiSi

Si channel

poly

NiSi NiSi

HfSiO/TiN

spac

er

NiSi

Si channel

poly

NiSi NiSi

HfSiO/TiN

spac

erMetal Gate - TiN

IMEC/Belgium:

Gate dielectric : 1 nm SiO2 chemical oxide2.3 nm MOCVD HfSiOtoxb = 150nmHfin = 65nmNa = 1x1015 cm-3

Metal Gate – TiN

2nm (64 ALD cycles)5nm (160 ALD cycles)

10nm (320 ALD cycles)

n type MuGFETs

10 finsWfin = 2, 1, 0.5, 0.2, 0.17mWfin,eff = Wfin - 0.13mmL = 10m

*I. Ferain et al., ESSDERC, p. 202-205, 2008.



Thinner TiN reduces slightly the onset of GIFBE

IG

Back interface accumulated (Fully depleted) to see GIFBE

VT increases

VT decreases

Thinner TiN metal gate

VFB

eWF

*Rodrigues M, Martino JA, Collaert N, Mercha A, Simoen E, Claeys C (2009)EuroSOI 2009



Devices Characteristics – Gate Stackn type MuGFETs

•Wfin = 2m

•10 fins•L = 10m

•toxb = 145nm

•Hfin = 65nm

•Na = 1x1015 cm-3

REF(1) (2) (3) (4) (5)

NiSi

Si channel

poly

NiSi NiSi

HfSiO/TiN

spac

er

NiSi

Si channel

poly

NiSi NiSi

HfSiO/TiN

spac

er

1 nm RTO (IL)

2.3nm HfSiO

PE-ALD TiN

Poly-Si

TiN

HfSiO

SiO2

5nm Dy2O3 Cap Layer HfSiO

SiO2

HfSiO

SiO2

2nm

3nm

Poly-Si

1 nm

Poly-Si

HfSiO

SiO2

Poly-Si

HfSiO

SiO2

4 nm

1 nm

1 nm

Poly-Si

HfSiO

SiO2

Poly-Si

HfSiO

SiO2

1 nm

4 nm

0.5 nm

Poly-Si

HfSiOSiO2

5 nm

0.5 nm

IMEC/Belgium:

*VLSI Symp. Dig. Techn. Papers, p. 14 (2008)- IMEC process



Gate Stack Influence on gm (*)*Martino JA, et al (2009), SOI Symposium, ECS Transactions.

VT

(eWF)

GIFBE (higher VGF)( IG)



0 1 2 3 4 50

10

20

30

40

50

NA= 5 x 1019 cm-3

Triple-Gate FinFET

g m (S

)

VGF (V)

0 1 2 3 4 5

0

20

40

60

80NA= 5 x 1019 cm

-3

(dgm

/ dV

G)

(A

/ V

2 )

Triple-Gate FinFET

VT,SGVT,TG

VT,TCVT,BC

VGF

(V)0 1 2 3 4 5

0

20

40

60

80

100

NA= 5 x 1019 cm-3

Triple-Gate FinFET

I D

S)

VG (V)

FinFET/Tri-Gate Technology (High NA) (*)

*Andrade MGC, Martino JA (2008), Solid-State Electronics, 52, 1877–1883.



0 1 2 3 4 5

0

20

40

60

80 NA= 5 x 1019 cm-3

(dgm

/ dV

G)

(A

/ V

2 )

Triple-Gate FinFET

VG (V)

VT,SGVT,TG

VT,TCVT,BC

Higher NA - three peaks are observed.

VT,TC : Top Corners

VT,BC : Bottom Corners

VT,SG VT,TG :Sidewall and Top

surfaces at the same time

FinFET/Tri-Gate Technology (High NA)

28

• Uso de isolantes de porta com alta constante dielétrica e/ou uso de Múltiplas Portas (FinFET)

• Incrementar a corrente (Silício tensionado, SiGe, Ge, Múltiplas Portas (FinFET)).

• Modificar a estrutura do MOSFET para melhorar o acoplamento eletrostático: MOS conv.SOI Múltiplas Portas (FinFET)

Para seguir a Lei de Moore é necessário:Para seguir a Lei de Moore é necessário:

CONCLUSÕESCONCLUSÕES

29

• Jean-Pierre Colinge

• Alunos de Mestrado e Doutorado da EPUSP.

• Colegas Professores e Doutores da USP, FEI e UNICAMP.

• FAPESP: Projeto Temático

• CNPq – INCT-NAMITEC : Prof. Jacobus Swart

AgradecimentosAgradecimentos

1 flutuação de dopantes efeitos quánticos problemas variação do v th intersubband scattering

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