redução da potência de uma interface de alta velocidade em...

\

Redução da potência de uma interface de alta velocidade em tecnologia CMOS através de "power gating"

Weekly Reports

Dissertação 2012/13 Luis Gomes Weekly Reports

Gantt Chart

Luis Gomes Weekly Reports

Dissertação 2012/13

2

Report N.º: 1 Week 18/02/2013 to 22/02/2013 Planed vs Performed work: • Synthesis workshop documentation read √ • Workstation configured √

Aditional Work (not planned) • Access Card PIN code memorized

Comments: None



3

Report N.º: 2 Week 25/02/2013 to 01/03/2013 Planed vs Performed work: • Read the following documentation:

• Welcome Pack: Synthesis.pdf √ • Welcome Pack: Place and route.pdf √ • Project Directory Structure √ • IC Compiler Workshop: Student Guide √

Aditional Work (not planned): None

Comments: None



4

Report N.º: 3 Week 04/03/2013 to 08/03/2013 Planed vs Performed work: • Complete a PLL HARDIP design flow using Synopsys tools √


Comments:

• Tools: • Synthesis – Design Compiler • Place and Route – IC Compiler • Logic Verification – Formality • Parasitic Extraction – Star-RCXT • Static Timing Analysis – Prime Time • Power Analyses – PrimeTime PX • IR Drop/EM analysis – Prime Rail • LVS/DRC – Hercules



5

Report N.º: 4 Week 11/03/2013 to 15/03/2013 Planed vs Performed work: • Document the 1st stage - Tools √ • Study M-PHY (MIPI) related documents √


Comments: None



6

Report N.º: 5 Week 18/03/2013 to 22/03/2013 Planed vs Performed work: • Gather M-PHY RX data (area, gate count, power, etc. ) • First version of the website √

Aditional Work (not planned)

• More M-PHY documentation was read √ • M-PHY RTL was studied √ • DesignWare POK- Power Optimization Kit (Power Optimization cells) documentation was read √ • Standard cells library documentation was read √ • Read more information on the book LPMM and ICC user guide in order to understand

how to define power islands and use POK cells. √

Comments: • Still some problems figuring how to attack the problem • Missing M-PHY RX post-layout data (the entire MPHY RX project is not available yet)

Luis Gomes

Weekly Reports Dissertação 2012/13

7

Report N.º: 6 Week 25/03/2013 to 30/03/2013 Planed vs Performed work:

• Further Analyze the RTL; √ • Start RTL modifications. √

Aditional Work (not planned)

• Unified Power Format (UPF) indentified as the best way to describe the desgin power intent. (including Power Gating elements).

Comments: • A new block featuring two multiplexers was described at RTL level. It allows choosing SoC

control signals instead of the MRX Lane digital control signals, when the latter is powered off.



8


• Describe the multiplexers power intent using UPF; √ • Synthesize the design and understand how Design Compiler interprets power intent and

infers power elements, such as level shifters, power switches, and isolation cells; • Extend UPF description to the rest of the design.

Aditional Work (not planned) • Study and understand how ICC supports power islands creation and switch cells insertion,

using UPF power intent description.

Comments: • The first objective was established as the isolation of the block mrxlanedig (considering it

as a macro cell). A power island needs to be created as isolated using a ring of power switches. In order to do so, design compiler flow will be skipped since power switches and voltage areas are inserted in ICC.



9


• Describe the toplevel MPHYGRXTYPE1 power intent using UPF √ • Adapt the toplevel RTL code. The only subblock has to be mrxlandedig √ • Create power domain and voltage area for macro cell mrxlanedig √ • Create a ring of power switches √ • Logically connect the power switches enable signal √

Aditional Work (not planned) • Research and study of documents related with the ICC multivoltage/multisupply flow .

Comments:



10


• Continue the study of documents related with ICC multivoltage/multisupply flow √ • Logically connect the power ports/pins in the design. √ • Understand how to automatically synthesize the power network taking into account the

existence of voltage areas and power switches. √

Aditional Work (not planned) • None

Comments:

• The UPF description elaborated in the previous week was wrong. The power switches and

the primary power net of the switchable domain must be created in the top domain. • Automatic logical connection of power ports/pins is achieved with derive_pg_connection

command • Automatic power network synthesis can be done using the synthesize_fp_rail command

with the voltage area option. In order to do it, the power network synthesis constraints have to first be first defined for each voltage area.



11


• Create a floorplan for the design. √ • Create a new FRAM view of mrxlanedig with its power pins spread around the macro. √ • Insert the multiplexers block and synthesize the design. √ • Create voltage areas, power switch ring and synthesize power network.

Aditional Work (not planned) Comments:

• Voltage areas and power switch ring created, but problems with the AFE (analogue) library

delayed the power network synthesis.



12


• Fix the problems related with the AFE library. √ • Synthesize the power network. √ • Analyze the results. Aditional Work (not planned) Comments:

• The automatic power network synthesis using sinthesize_fp_rail command doesn’t provide good results. The power network was planned and created “manually”



13


• Complete the physical implementation flow (route, insert tap calls, insert filler cells) • Perform DRC and LVS analyses. • Analyze the results. Aditional Work (not planned) Comments:



14

redução da potência de uma interface de alta velocidade em...

Documents