lc voltage controlled oscillators · lc voltage controlled oscillators . dissertação para...

Pedro Miguel Ribeiro Pereira

Mestre

Optimization Based Design of LC Voltage Controlled Oscillators

Dissertação para obtenção do Grau de Doutor em Engenharia Electrotécnica e de Computadores

Orientador: Prof. Doutora Maria Helena Fino, Professora Auxiliar, Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa

Co-orientador: Prof. Doutor Mário Ventim Neves, Professor Auxiliar, Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa

Júri: Presidente: Prof. Doutor Paulo da Costa Luís da Fonseca Pinto

Arguentes: Prof. Doutor Francisco Vidal Fernández Fernández Prof. Doutor João Manuel Torres Caldinhas Simões Vaz

Vogais: Prof. Doutor Mourad Fahkfahk Prof. Doutor Fernando José Almeida Vieira Coito

Maio, 2013

Optimization Based Design of LC Voltage Controlled Oscillators

Copyright © Pedro Miguel Ribeiro Pereira, Faculdade de Ciências e Tecnologia, Univer-sidade Nova de Lisboa.

A Faculdade de Ciências e Tecnologia e a Universidade Nova de Lisboa têm o direito, perpétuo e sem limites geográficos, de arquivar e publicar esta dissertação através de exem-plares impressos reproduzidos em papel ou de forma digital, ou por qualquer outro meio conhecido ou que venha a ser inventado, e de a divulgar através de repositórios científicos e de admitir a sua cópia e distribuição com objectivos educacionais ou de investigação, não comerciais, desde que seja dado crédito ao autor e editor.

The Faculdade de Ciências e Tecnologia and the Universidade Nova de Lisboa have a right, perpetual and without geographical limits, of filing and publishing this dissertation through printed examples reproduced in paper or in the digital form, or for any other known way or that might be invented, and of spreading it through scientific repositories and of admit-ting its copy and distribution with education or investigation objectives, without commercial in-tents, as credit is given to the author and publisher.

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Acknowledgments

I would like to take this opportunity to remember, in an informal way, those who in many different ways have supported me during the long years that I took to complete this work.

Sincerely, I am deeply grateful to my supervisor, Professor Helena Fino, for her support, guidance, professionalism, patience and knowledge, both scientific and intellectual. Without her enthusiasm and insights, priceless comments and discussions, probably most of this work would not have been possible. I will be forever grateful.

I would like to thanks to my co-supervisor, Professor Ventim-Neves, for his useful ad-vices when I faced less optimistic moments. I will never forget some of his history lessons during countless enjoyable lunches.

I also would like to express my sincere thanks to Professor Fernando Coito, for his valuable comments throughout some periods of my research. The joint work that has resulted from our close collaboration, was fruitful.

A special word of appreciation goes to Professor Leão Rodrigues, for opening me the door of the academic world, but mostly for his delightful lectures and teachings during my time as student, that have made me embrace this career. To him, my most sincere recognition.

I wish to express my sincere thanks to Professor Mourad Fakhfakh, Amin Sallem and Mouna Kotti, from University of Sfax – Tunisia, for their collaboration through this last years, and for their valuable input on my research.

I would like to say “thanks” to all the colleagues of my group. Those who daily knocked on my office door, inviting me for a coffee or just for five minutes of talking, deserve a special word of appreciation. Many thanks to João (Pina), who has a great sense of humour that im-proves a lot the working environment. Day by day, he became more than a colleague. A big

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thanks to Anabela, who started as my teacher and over time became a good friend – I would like to thank her for her support and friendship. The other João (Martins), the most recent member of the group, but rapidly has proved to be a cool fellow. To him, my genuine friend-ship. Last, I would like to mention David, for his friendship and support.

There are friends that no matter where they are, we can count on them. Fortunately, I have two of those friends: Raquel and Agostinho. I am forever grateful for their patience lis-tening me.

A special thanks to my family. Without their love, support and encouragement during this path would have been harder. I would like to say sorry to little Diogo, for all the time and patience that at times I did not have for him. Although, he has always been present when I needed him. Thanks for every smile.

Finally, I would like to acknowledge the financial support from the Portuguese National Funding Agency through the Fundação para a Ciência e Tecnologia (FCT - Science and Technology Foundation) PEst-OE/EEI/UI0066/2011 project.

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Abstract

As result of the progress in technology development and the use of submicron CMOS processes, digital circuits have become faster and more precise, and with decreased imple-mentation area. This technological improvement enforces more restricted specifications in terms of gain, phase noise and size for the analog/RF counterparts.

Due to the high-density integration needs as well as to low cost fabrication, fully inte-grated LC-VCOs applied to RF applications, such as clock generation, frequency synthesizers or timing-recovery circuits are usually implemented in CMOS technology. Thus, nowadays the challenge of analog/RF design task is to design a circuit to accomplish very stringent design specifications in terms of phase-noise, power consumption or area, among others, must be attained, leading to the necessity of finding design solutions where technology is pushed to-wards its limits.

Nonetheless, the technology scaling has lead to a decrease in the supply voltage, thus making the analogue design more challenging, since neither a wide range of linearity nor full output voltage swing are easily guaranteed. In the particular case of LC-VCOs, since their design involves some trade-offs and relies on the estimation of several parameters, which can be correlated. Traditional hand-calculation design methods are not an option when CMOS submicrometer technology is being used. Moreover, simulation based optimization, which is generally the most accurate design procedure, can become prohibitive, since is an extremely time consuming process. To cope with the complexity of the design, optimization based meth-odologies must be adopted. For the efficiency of the design process, analytical models for both passive and active devices must be considered.

To accomplish the goal proposed for this thesis, emphasis is placed on identifying the most suitable analytical models that accurately characterize the behaviour of each single ele-ment in the LC-VCO. These models, which must rely on technological parameters, in opposi-

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tion to those based in fitting parameters supported by an exhaustive simulation process, are a fundamental key for an optimization based design procedure, that aims to be simulation inde-pendent. Such kind of analytical models, allow to understand the device physics and to apply it successfully for the analog/RF design purposes.

To achieve the LC-VCO design optimization goals, evolutionary algorithms, namely the genetic algorithms, are used. Due to the different kind of nature of the problem under analy-sis, the optimization process is able to deal with discrete and continuous variables as well as constrained search space. Moreover, this optimization technique help designers dealing with design trade-offs, such as phase noise and power consumption, in an intuitive way, avoiding the blind believe in simulators.

The performance of the LC voltage controlled oscillator, designed by the proposed opti-mization-based design tool, gives fairly acceptable results when compared with those obtained through commercial simulators. It proves that the proposed tool is a good design instrument for a first approach design, as intended to be.

Keywords: LC-VCO; Accurate device models; Design methodology; Discrete-Variable

Optimization; Genetic Algorithms

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Resumo

O progresso no desenvolvimento de tecnologias submicrométricas em processo CMOS, possibilitou que os circuitos digitais se tornassem mais rápidos e mais precisos, e simulta-neamente levou a uma diminuição da área de implementação. Este avanço tecnológico nos circuitos digitais impõe especificações mais restritas, não só em termos de ganho e ruído de fase, mas também relativamente às dimensões físicas dos dispositivos analógicos/RF que com eles interagem.

Devido ao elevado nível de integração de dispositivos actualmente pretendido, aliado ao desejado baixo custo de produção, os osciladores controlados por tensão (LC-VCO) total-mente integrado para aplicações em RF, como sejam os geradores de frequência de relógio, sintetizadores de frequência ou circuitos de recuperação de relógio, são geralmente imple-mentados em tecnologia CMOS. Assim, o desafio de dimensionar dispositivos analógicos/RF é, hoje em dia, o de conceber um circuito que satisfaça especificações muito rigorosas em termos de ruído de fase, consumo de energia ou área de implementação, entre outros. Tais exigências conduzem à necessidade de encontrar soluções de dimensionamento onde, nor-malmente, a tecnologia é levada aos limites.

Por outro lado, o avanço tecnológico em direcção às tecnologias submicrométricas, tem levado a uma diminuição da tensão de alimentação dos circuitos, tornando assim o dimensio-namento dos dispositivos analógicos mais desafiante, uma vez que quer a linearidade dos circuitos, quer uma habitual elevada amplitude da tensão de saída não são facilmente garan-tidas. No caso particular de um LC-VCO, uma vez que o seu dimensionamento abraça ques-tões de compromisso (trade-offs), p. ex. ruído de fase vs consumo, além de se apoiar na avaliação de vários parâmetros, correlacionados entre si, os métodos tradicionais de dimen-sionamento baseados em cálculos analíticos aproximados, não são de todo uma opção aquando do uso de tecnologias submicrométricas CMOS. Nestas situações, o dimensiona-

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mento por recurso a simulação, que é geralmente o procedimento de dimensionamento mais rigoroso, mostra ser um processo que consome muito tempo e que poderá tornar-se proibiti-vo. Para lidar com a complexidade de projecto de circuitos analógicos, deverão ser adoptadas metodologias de dimensionamento baseadas em mecanismos de optimização. De forma a melhorar o processo de dimensionamento, devem ainda ser considerados modelos analíticos precisos, que caracterizem o comportamento quer dos elementos passivos quer dos elemen-tos activos envolvidos.

Para alcançar o objetivo proposto neste trabalho, numa primeira fase é colocada ênfase na identificação dos modelos analíticos mais adequados para a caracterização, com razoável precisão, do comportamento de cada dispositivo do LC-VCO. Estes modelos, que devem apoiar-se em parâmetros tecnológicos, em oposição aos baseados em parâmetros obtidos por recurso a processos de simulação exaustivos, são indispensáveis para um dimensionamento baseado em metodologias de optimização. Por outro lado, tais modelos analíticos permitem ao projectista ter sensibilidade para os parâmetros que determinam o comportamento do dis-positivo, e assim serem aplicados com sucesso para fins de dimensionamento de circuitos analógicos/RF.

O presente trabalho propõe uma ferramenta de dimensionamento de LC-VCOs, por recurso a uma estratégia de optimização baseada em algoritmos genéticos, de forma a garantir que as especificações de desempenho do circuito sejam garantidas. Devido à nature-za do problema em análise, o processo de otimização é capaz de lidar quer com variáveis discretas quer com variáveis contínuas, assim como com espaços de procura condicionados por restrições tecnológicas ou de especificações de performance. A ferramenta de dimensio-namento aqui proposta possibilita ainda de uma forma ágil, inferir o comportamento do circuito quando sujeito a variações dos parâmetros de dimensionamento.

Os dispositivos (LC-VCOs) projectados pela ferramenta proposta, apresentam um desempenho bastante aceitável relativamente a diversas características de funcionamento, tais como a frequência de oscilação, ruído de fase e consumo, quando comparado com os resul-tados obtidos através de simuladores comerciais.

Palavras-chave: LC-VCO; Modelos precisos de dispositivos; Metodologia de dimensio-

namento; Optimização de variáveis discretas; Algoritmos Genéticos

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Table of Contents

Acknowledgments .................................................................................................................... vii

Abstract .................................................................................................................................... ix

Resumo.................................................................................................................................... xi

Table of Contents .................................................................................................................. xiii

List of Figures ....................................................................................................................... xvii

List of Tables ......................................................................................................................... xxi

List of Symbols ..................................................................................................................... xxv

Acronyms ............................................................................................................................. xxix

1 Introduction ...................................................................................................................... 31 1.1 Motivation and Background ......................................................................................... 31 1.2 Problem Formulation .................................................................................................. 37

1.2.1 Research Question ........................................................................................ 39 1.3 Contributions .............................................................................................................. 39

1.3.1 Other Related Publications ............................................................................ 44 1.4 Chapter by Chapter Overview .................................................................................... 45

2 Background on VCO Design and Optimization Methodologies ........................................ 47 2.1 Introduction ................................................................................................................ 47 2.2 Early Work ................................................................................................................. 49 2.3 Conclusions ............................................................................................................... 54

3 CMOS Transistor Model .................................................................................................. 57 3.1 Introduction ................................................................................................................ 57 3.2 EKV MOS Transistor Model ....................................................................................... 59

Table of Contents

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3.2.1 EKV Model Parameters Extraction ................................................................. 60 3.2.2 Parameters Extraction - Example .................................................................. 63

3.3 Integrated Capacitors - Varactors .............................................................................. 67 3.3.1 CMOS Varactor Model ................................................................................... 71

3.4 Applicability of the Model to RF Frequencies ............................................................. 73 3.5 Conclusions ............................................................................................................... 75

4 Spiral Inductor ................................................................................................................ 77 4.1 Introduction ................................................................................................................ 77 4.2 Lumped Elements Analytical Characterization ............................................................. 81

4.2.1 Inductance (Ls) Models .................................................................................. 81 4.2.1.1 Greenhouse Approximation of Grover Formulae ................................ 82 4.2.1.2 Modified Wheeler Formula ................................................................ 82 4.2.1.3 Data Fitted Monomial Expression ...................................................... 82 4.2.1.4 Current Sheet Approximation ............................................................. 83 4.2.1.5 Jenei Approximation of Grover Formulae .......................................... 83

4.2.2 Inductor Resistance, Rs ................................................................................. 84 4.2.3 Crossover Capacitance, Cs ............................................................................ 84 4.2.4 Oxide Capacitance, Cox ................................................................................. 85 4.2.5 Substrate Resistance (Rsi) and Capacitance (Csi) ......................................... 85 4.2.6 Inductor Quality Factor (Q) ........................................................................... 85 4.2.7 Model Validation ............................................................................................ 88

4.3 Inductor Double-π model ........................................................................................... 90 4.3.1 DC inductor parameters .................................................................................. 91

4.3.1.1 Metal-to-metal capacitance, Cc .......................................................... 91 4.3.2 Substrate Network ......................................................................................... 92 4.3.3 Ladder Circuit Elements ................................................................................ 93 4.3.4 Quality Factor Evaluation ............................................................................... 94 4.3.5 Model Validation ............................................................................................ 95

4.4 Conclusions ............................................................................................................... 97

5 VCO Tank Optimization .................................................................................................. 99 5.1 Introduction ................................................................................................................ 99 5.2 Optimization Approaches .......................................................................................... 103

5.2.1 Optimization Methods ................................................................................... 105 5.2.1.1 Evolutionary Algorithms .................................................................... 106

5.3 Integrated Inductor Optimization-Based Design ......................................................... 109 5.3.1 Optimization Methodology for Inductor Design .............................................. 110

5.3.1.1 Main characteristics of the inductor design ........................................ 111 5.3.1.2 Genetic Algorithms ........................................................................... 112

Table of Contents

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5.3.2 Inductor Design ............................................................................................ 114 5.3.2.1 Continuous vs Discrete Variable Optimization................................... 115 5.3.2.2 Discrete-Variable Optimization Examples ......................................... 118

5.3.3 Sensitivity Analysis ....................................................................................... 121 5.3.3.1 Sensitivity Analysis Applied to Inductor Design ................................. 123

5.4 Varactor Optimization-based Design ......................................................................... 124 5.4.1 Varactor Design ............................................................................................ 127

5.5 Conclusions .............................................................................................................. 128

6 LC-VCO Design ............................................................................................................. 131 6.1 Introduction ............................................................................................................... 131 6.2 LC-VCO Characterization .......................................................................................... 133 6.3 LC-VCO Optimization Strategy.................................................................................. 137

6.3.1 LC-VCO Design: Optimization Approach ...................................................... 139 6.4 Results and Discussion .............................................................................................140

6.4.1 LC-VCO Simple Approach Optimization ........................................................ 142 6.4.1.1 LC-VCO Design - 1.0 GHz .............................................................. 143 6.4.1.2 LC-VCO Design - 1.5 GHz .............................................................. 146 6.4.1.3 LC-VCO Design - 2.0 GHz ............................................................. 147 6.4.1.4 LC-VCO Design - 2.4 GHz ............................................................. 149 6.4.1.5 LC-VCO Design - 2.8 GHz .............................................................150

6.4.2 LC-VCO Moderate Approach Optimization .................................................... 152 6.4.2.1 LC-VCO Design - 1.0 GHz .............................................................. 152 6.4.2.2 LC-VCO Design - 2.0 GHz ............................................................. 154 6.4.2.3 LC-VCO Design - 2.8 GHz ............................................................. 155

6.4.3 LC-VCO Hard Approach Optimization ........................................................... 157 6.4.3.1 LC-VCO Design - 1.0 GHz .............................................................. 157 6.4.3.2 LC-VCO Design - 2.0 GHz ............................................................. 159 6.4.3.3 LC-VCO Design - 2.8 GHz ............................................................. 161

6.5 Conclusions .............................................................................................................. 162

7 Conclusions ................................................................................................................... 165 7.1 Summary of Contributions ......................................................................................... 167 7.2 Suggestions for Future Work .................................................................................... 167

References ............................................................................................................................ 169

Appendix I ............................................................................................................................. 179

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List of Figures

Figure 1.1: VCO design trade-offs .......................................................................................... 32 Figure 1.2: NMOS LC-VCO ................................................................................................... 34 Figure 1.3: Double switch LC-VCO ........................................................................................ 35 Figure 1.4: Analog Design characteristics: simulation vs analytical tools ................................ 36 Figure 2.1: Digital vs analog design ....................................................................................... 48 Figure 2.2: General overview of an optimization-based design .............................................. 53 Figure 2.3: Chronological map regarding the State-of-the-art of LC-oscillators design .......... 53 Figure 3.1: Flowchart of the BSIM to EKV model extraction parameters ................................. 61 Figure 3.2: EKV model - IS parameter extraction ................................................................... 62 Figure 3.3: EKV model - pinch-off voltage (VP) parameter extraction ................................... 62 Figure 3.4: EKV model - parameter extraction, VP as function of Vg ..................................... 63 Figure 3.5: Transistor Ids error between EKV model and simulation (HSPICE) results........... 64 Figure 3.6: Ids error between EKV model and simulation (HSPICE) results for L=const and

W=variable .................................................................................................................... 65 Figure 3.7: Ids error between EKV model and simulation (HSPICE) results for L= variable

and W=const. ................................................................................................................ 66 Figure 3.8: Ids error between EKV model and simulation (HSPICE) results for L and W

variable .......................................................................................................................... 67 Figure 3.9: CMOS Varactor ................................................................................................... 68 Figure 3.10: Tuning characteristics for a PMOS capacitor (B=D=S) ...................................... 68 Figure 3.11: PMOS varactor ................................................................................................... 69 Figure 3.12: Tuning characteristics for an I-MOS varactor [39] ............................................ 69 Figure 3.13: Tuning characteristics for an A-MOS varactor [39] ........................................... 70 Figure 3.14: MOS transistor capacitances ............................................................................... 71 Figure 3.15: Tuning characteristics for an I-MOS varactor ..................................................... 73

List of Figures

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Figure 3.16: Overview of the several ways to develop electrical models for circuit simulators [47] ............................................................................................................................... 74

Figure 4.1: The photomicrograph of an LC-VCO [51] ............................................................ 78 Figure 4.2: Integrated spiral inductor: a) Planar inductor simple-π model, b) Single metal

layer topology ................................................................................................................. 79 Figure 4.3: Integrated spiral inductor: a) modified model [57], b) substrate coupled model

[59] ............................................................................................................................... 80 Figure 4.4: Comparison between complexity vs accuracy of different inductor models ........... 80 Figure 4.5: Layout parameters of a square inductor ............................................................... 81 Figure 4.6: Inductor behaviour vs frequency ........................................................................... 86 Figure 4.7: One port π model circuit: a) One port π model, b) One port equivalent circuit .... 86 Figure 4.8: Square planar inductor ......................................................................................... 88 Figure 4.9: Spiral inductor inductance, π model vs ASITIC .................................................... 89 Figure 4.10: Spiral inductor resistance, π model vs ASITIC .................................................... 89 Figure 4.11: Spiral inductor reactance, π model vs ASITIC ..................................................... 89 Figure 4.12: Spiral inductor quality factor, π model vs ASITIC ................................................ 90 Figure 4.13: Inductor double-π model equivalent circuit .......................................................... 91 Figure 4.14: Cross section of a planar inductor ...................................................................... 91 Figure 4.15: The basic metal-oxide-silicon structure and its equivalent circuit. ....................... 93 Figure 4.16: 2 GHz Spiral inductor inductance, double-π model vs ASITIC ............................ 96 Figure 4.17: 2 GHz Spiral inductor quality factor, double-π model vs ASITIC ........................ 96 Figure 4.18: 6 GHz Spiral inductor inductance, double-π model vs ASITIC ............................ 96 Figure 4.19: 6 GHz Spiral inductor quality factor, double-π model vs ASITIC ........................ 97 Figure 5.1: LC tank circuit ..................................................................................................... 100 Figure 5.2: Optimization methods ......................................................................................... 105 Figure 5.3: Stochastic search methods ................................................................................. 106 Figure 5.4: Genetic Algorithm procedure flowchart................................................................ 108 Figure 5.5: Particle Swarm Optimization procedure flowchart................................................ 108 Figure 5.6: Layout of a square inductor ................................................................................. 110 Figure 5.7: General architecture for an optimization design approach.................................... 112 Figure 5.8: Basic Genetic Algorithm Optimization Flowchart .................................................. 113 Figure 5.9: Inductance and quality factor for the designed Inductor ...................................... 120 Figure 5.10: Inductance in the vicinity of the designed Inductor ........................................... 120 Figure 5.11: Quality factor in the vicinity of the designed Inductor ......................................... 121 Figure 5.12: Process variables impact on inductor quality factor and inductance .................. 122 Figure 5.14: NMOS inversion-mode varactor ........................................................................ 125 Figure 5.15: Varactor optimization-based design flowchart .................................................... 126 Figure 5.16: Capacitance behaviour for the designed varactor .............................................. 128

List of Figures

xix

Figure 6.1: Circuit schematic of an LC-VCO ......................................................................... 132 Figure 6.2: Double-switch LC-VCO with a current source .................................................... 133 Figure 6.3: Double-switch LC-VCO with parasitic elements .................................................. 135 Figure 6.4: Flowchart of the LC-VCO design tool ................................................................. 137 Figure 6.5: LC-VCO optimization design flowchart ................................................................ 138 Figure 6.6: LC-VCO design: Optimization Approach ............................................................. 140 Figure 6.7: LC-VCO output signal (Vout1 and Vout2) @ 1.0 GHz ............................................ 144 Figure 6.8: Phase noise evolution through each generation .................................................. 145 Figure 6.9: Oscillation frequency evolution through each generation ..................................... 146 Figure 6.10: LC-VCO output signal (Vout1 and Vout2) @ 1.5 GHz .......................................... 147 Figure 6.11: LC-VCO output signal (Vout1 and Vout2) @ 2.0 GHz .......................................... 148 Figure 6.12: LC-VCO output signal (Vout1 and Vout2) @ 2.4 GHz .......................................... 150 Figure 6.13: LC-VCO output signal (Vout1 and Vout2) @ 2.8 GHz ...........................................151 Figure 6.14: LC-VCO output signal (Vout1 and Vout2) @ 1.0 GHz .......................................... 153 Figure 6.15: LC-VCO output signal (Vout1 and Vout2) @ 2.0 GHz.......................................... 155 Figure 6.16: LC-VCO output signal (Vout1 and Vout2) @ 2.8 GHz .......................................... 156 Figure 6.17: LC-VCO output signal (Vout1 and Vout2) @ 1.0 GHz .......................................... 159 Figure 6.18: LC-VCO output signal (Vout1 and Vout2) @ 2.0 GHz.......................................... 160 Figure 6.19: LC-VCO output signal (Vout1 and Vout2) @ 2.8 GHz .......................................... 162

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List of Tables

Table 1.1: VCO design specifications for RF applications ....................................................... 33 Table 2.1: Published VCO’s characteristics ............................................................................ 54 Table 3.1: EKV model parameters (L=0.39µm and W=50L) ................................................. 63 Table 4.1: Integrated inductor layout parameters ..................................................................... 81 Table 4.2: Modified Wheeler Formula coefficients .................................................................. 82 Table 4.3: Data Fitted Monomial Expression coefficients ....................................................... 83 Table 4.4: Current Sheet Approximation coefficients .............................................................. 83 Table 4.5: Square planar inductor dimensions ....................................................................... 88 Table 4.6: Square planar inductor dimensions (4 nH @ 2-6 GHz)....................................... 95 Table 5.1: Simulation and equation-based optimization ......................................................... 103 Table 5.2: Comparison between simulation and equation-based approaches ........................ 104 Table 5.3: Physical parameters of inductor design .................................................................114 Table 5.4: Design constraints ................................................................................................115 Table 5.5: Optimization results for minimum tolerance ...........................................................116 Table 5.6: Final inductance and % error for several solutions ...............................................116 Table 5.7: Final results for minimum tolerance with discrete-variable optimization .................117 Table 5.8: Comparison of results between evaluated and simulated ....................................117 Table 5.9: Optimization results for maximum Q .....................................................................117 Table 5.10: Final inductance and % error for several solutions ..............................................117 Table 5.11: Final results for minimum tolerance with discrete-variable optimization ................118 Table 5.12: Comparison of results between evaluated and simulated ..................................118 Table 5.13: Optimization results for a square inductor of 5 nH (Dout max of 200 µm) and

its comparison with ASITIC simulations .........................................................................119 Table 5.14: Optimization results for a square inductor of 7 nH (Dout max of 250 µm) and

its comparison with ASITIC simulations .........................................................................119

List of Tables

xxii

Table 5.15: Optimization results for an inductor of 5 nH @ 0.7 GHz ................................... 123 Table 5.16: Optimization results for an inductor of 5 nH @ 1.0 GHz ................................... 123 Table 5.17: Sensitivity to variations in oxide (tox) and metal thickness (t) ............................ 124 Table 5.19: Varactor technological-physical parameters and optimization constraints ............ 127 Table 5.20: Optimization results and its comparison with HSPICE simulations ..................... 128 Table 6.1: Inductor and transistor technological-physical parameters ..................................... 141 Table 6.2: LC-VCO design constraints ................................................................................. 142 Table 6.3: Design parameters range .................................................................................... 142 Table 6.4: LC-VCO design characteristics (Simple Approach) ............................................. 143 Table 6.5: LC-VCO transistors sizes .................................................................................... 143 Table 6.6: Resonator elements size (1.0 GHz) .................................................................... 143 Table 6.7: Optimization design results vs simulation (1.0 GHz) ........................................... 144 Table 6.8: Resonator elements size (1.5 GHz) .................................................................... 146 Table 6.9: Optimization design results vs simulation (1.5 GHz) ........................................... 146 Table 6.10: Resonator elements size (2.0 GHz) .................................................................. 148 Table 6.11: Optimization design results vs simulation (2.0 GHz) .......................................... 148 Table 6.12: Resonator elements size (2.4 GHz) .................................................................. 149 Table 6.13: Optimization design results vs simulation (2.4 GHz) ......................................... 149 Table 6.14: Resonator elements size (2.8 GHz) .................................................................. 150 Table 6.15: Optimization design results vs simulation (2.8 GHz) .......................................... 151 Table 6.16: LC-VCO design characteristics (Moderate Approach) ........................................ 152 Table 6.17: VCO elements size (1.0 GHz) ........................................................................... 153 Table 6.18: Optimization design results vs simulation (1.0 GHz) .......................................... 153 Table 6.19: VCO elements size (2.0 GHz) .......................................................................... 154 Table 6.20: Optimization design results vs simulation (2.0 GHz)......................................... 155 Table 6.21: VCO elements size (2.8 GHz) .......................................................................... 156 Table 6.22: Optimization design results vs simulation (2.8 GHz) ......................................... 156 Table 6.23: LC-VCO design characteristics .......................................................................... 157 Table 6.24: Resonator’s dimensions (1.0 GHz) ................................................................... 158 Table 6.25: Active elements size (1.0 GHz) ........................................................................ 158 Table 6.26: Optimization design results vs simulation (1.0 GHz) ......................................... 158 Table 6.27: Resonator’s dimensions (2.0 GHz) ................................................................... 159 Table 6.28: Active elements size (2.0 GHz) ........................................................................ 159 Table 6.29: Optimization design results vs simulation (2.0 GHz) ......................................... 160 Table 6.30: Resonator’s dimensions (2.8 GHz) .................................................................... 161 Table 6.31: Active elements size (2.8 GHz) ......................................................................... 161 Table 6.32: Optimization design results vs simulation (2.8 GHz) .......................................... 161 Table 6.33: Overview of the optimization design results vs simulation (1.0 GHz) ................ 163

List of Tables

xxiii

Table 6.34: Overview of the optimization design results vs simulation (2.0 GHz) ................ 163 Table 6.35: Overview of the optimization design results vs simulation (2.8 GHz) ................ 164

xxv

List of Symbols

Θ Mobility reduction coefficient

γ Body effect parameter

φ Bulk Fermi potential

σ Metal conductivity

δ Skin depth in AC currents (skin effect)

γ’ Corrected body effect parameter

β0 Transconductance - EKV transistor model parameter

ε0 Permittivity of free space

µ0 Magnetic permeability of vacuum

εr Relative permittivity of silicon

σsi Inductor substrate conductivity

CDB CMOS transistor drain-bulk capacitance

Cextrinsic CMOS transistor extrinsic capacitances

CGB CMOS transistor gate-bulk capacitance

CGD CMOS transistor gate-drain capacitance

CGS CMOS transistor gate-source capacitance

Cif CMOS transistor inner fringing capacitance

Cof CMOS transistor outer fringing capacitance

Cov CMOS transistor gate overlap capacitance

List of Symbols

xxvi

Cox CMOS transistor gate-oxide capacitance

Cox Inductor metal track - substrate capacitance

Cs Inductor capacitance between metal tracks and underpass

CSB CMOS transistor source-bulk capacitance

Csi Inductor substrate capacitance

din Inductor inner diameter

dout Inductor outer diameter

f Oscillation frequency

gactive CMOS transistors conductance

Gsi Inductor substrate conductance per unit area

gtank Tank resonator conductance

hsi Inductor substrate height

Ids CMOS transistor current through drain to source

if CMOS transistor forward current

Ifor CMOS transistor normalized forward current

ir CMOS transistor reverse current

Irev CMOS transistor normalized reverse current

Is CMOS transistor specific current

l Inductor track length

L∆f Phase noise at a frequency ∆f in the vicinity of f

Leff CMOS transistor effective length

LETA CMOS transistor short channel effect coefficients

Ls Inductor DC inductance

n Slope factor - EKV transistor model parameter

Q Quality factor

Rs Inductor DC resistance

Rsi Inductor substrate resistance

t Inductor track thickness

List of Symbols

xxvii

Tox CMOS transistor oxide thickness

TR Tuning range

UT CMOS transistor thermal voltage

Vbulk CMOS transistor bulk voltage

Vd CMOS transistor drain voltage

Vg CMOS transistor gate voltage

Vg’ Corrected CMOS transistor effective gate voltage

VP CMOS transistor pinch-off voltage

VP’ Corrected CMOS transistor pinch-off voltage

Vs CMOS transistor source voltage

Vt0 CMOS transistor threshold voltage

Vtank Oscillator output voltage amplitude

w Inductor track width

Weff CMOS transistor effective width

WETA CMOS transistor narrow width effect coefficients

xxix

Acronyms

ACM Area Calculation Method - transistor model

BiCMOS Bipolar Complementary Metal Oxide Semiconductor

BJT Bipolar Junction Transistor

CAD Computer-Aided Design

CMOS Complementary Metal-Oxide-Semiconductor

EA Evolutionary Algorithms

EKV Enz, Krummenacher and Vittoz - transistor model

EM Electromagnetic simulator

FoM Figure of Merit

GA Genetic Algorithms

gm Transistor transconductance

GNP Graphical Nonlinear Programming

HSPICE Hailey Simulation Program with Integrated Circuit Emphasis

MGA Modified Genetic Algorithms

NMOS N-type Metal-Oxide Semiconductor

PMOS P-type Metal-Oxide Semiconductor

PN Phase Noise

PSO Particle Swarm Optimization

RF Radio Frequency

Acronyms

xxx

SPICE Simulation Program with Integrated Circuit Emphasis

SQP Sequential Quadratic Programming

UMC130 United Microelectronics Corporation – 130 nm

Varactor Variable capacitor

VCO Voltage Controlled Oscillator

VHDL-AMS Very High speed hardware Description Language - Analog and Mixed-Signal

31

1 Introduction

This chapter emphasizes the main issues addressed in this thesis. The chapter starts presenting the motivation that has lead to this work, and briefly gives an overview regarding the background on the subject. Issues that are still open concerning analog/RF design meth-odology are offered, as the base for the proposed research question. The expected and achieved contributions resulting from this work are presented. Finally, the chapter gives a de-scription of this thesis organization.

1.1 Motivation and Background

The worldwide market of communications systems circuits, such as clock generation, frequency synthesizers or timing-recovery circuits, is still growing exponentially. The demands for new communications services have motivated manufacturers competitiveness in order to provide equipments with higher performance and lower cost, than the previous generation. In fact, and assuming the prediction in [1], during the first decade of the XXI century, the goal for this market was to reduce both the power consumption and price of this devices by 30% every year. This demand has been pulled up, but not only, by the advances in wireless tech-nology that brought to mobile devices the challenge of incorporating in the same equipment a set of functionalities such as text, audio, video, web access, global position system (GPS) or smart handheld devices.

As result of the progress in technology development and the use of submicron CMOS processes, digital circuits have become faster and more precise, and with decreased of the implementation area. This technological improvement enforces more restricted specifications in terms of gain, phase noise and size for the analog/RF counterparts. Consequently, the design of analog/RF devices becomes more challenging, as recent technologies carry two major dif-ficulties: firstly, due to the reduction of the oxide thickness, parasitic capacitances increase; secondly, smaller output resistances are obtained, enforced by short channel-effects. Thus,

Introduction

32

the challenge of analog/RF design task nowadays is to design a circuit to accomplish the required specifications, at low supply voltage, (for low power consumption) and low phase noise, taken into account that transistors have more parasitic effects and less intrinsic gain. Moreover, the performance of an on-chip device is aimed to get closer to those achieved with an off-chip device. Therefore, there’s a question that always climbs at a designer’s mind, “How to size analog circuits to achieve the required performances?” [2].

In the particular case of RF systems, such as a receiver or a transceiver, RF circuits must process analog signals with a wide dynamic range at high frequencies, and the voltage controlled oscillator (VCO) is a critical element in the RF front-end block. The trade-off be-tween phase noise, oscillation frequency and power consumption are particularly demanding when aiming a fully integrated solution. The trade-offs involved in the design of such circuits can be summarised in Figure 1.1.

Figure 1.1: VCO design trade-offs

The wide variety of VCO applications in communications systems, working from some hundreds of MHz up to a few GHz, and motivated by the fact that transistors size have been scaled down, has lead to the full integration of the VCO in a chip. From manufacturers’ point of view, this new market demand is characterised by the Price-Package-Performance-Power, usually called as the P words.

An oscillator can be defined as a device that generates a periodically time-varying sig-nal. There are various forms of oscillator implementations, such as ring, LC tuned, crystal and relaxation oscillators. The typical specifications for a VCO design are summarised in Table 1.1 [3], and the most important are the centre frequency, the tuning range, the phase noise, the power supply voltage and the power consumption.

Introduction

33

Table 1.1: VCO design specifications for RF applications

Specification Unit

Centre Frequency GHz

Tuning Range MHz Phase Noise dBc/Hz @ offset [kHz]

Power consumption mW

Supply voltage V VCO gain MHz/V

Pullling MHz/load-specif.

Pushing MHz/V Area µm2

Cost €

Operating Temperature ºC Manufacturability

Yield %

Lifetime Years

Regarding the implementation of a fully integrated VCO, the usual choice goes to the ring, relaxation or LC oscillators. The first two, have a wide tuning range when compared with LC oscillators, as well as lower implementation area. However, LC oscillator shows better per-formance concerning phase noise and power consumption. Due to this, in those applications where lowest possible phase noise with low power dissipation is the driving issue, designers may decide to use LC oscillators [4]. Hence, they are extremely popular in RF applications.

The frequency of most RF oscillators must be adjustable. For that purpose, oscillators can be controlled either by voltage (called voltage controlled oscillators) or by current. Al-though current controlled oscillators are feasible, they are not used often due to difficulties in controlling the energy stored in the LC tank by current. Several topologies have been pro-posed in literature for VCOs implementation. The two most popular topologies are the Colpitts or the negative Gm oscillators, as they provide a negative resistance through a feedback loop, in order to reduce the losses in the circuit, consequently attaining better performance [5]. These topologies can be implemented either with bipolar or MOS transistors [4]. In this work, only the MOS version is considered, since CMOS technology is preferable for this category of circuits, due to their better performance with digital circuits, and less power dissipation when compared with BJT technology. Furthermore, due to their simplicity, CMOS oscillators based on controlling the negative Gm are the designers’ first choice.

LC-voltage controlled oscillators (LC-VCOs) can also have single or differential output. For RF oscillators the differential output is preferable since their common mode rejection char-acteristic provides better immunity to some noise sources. In Figure 1.2 and Figure 1.3 four typical LC-VCO implementations are represented.

Introduction

34

a) Current source to ground b) Current source to Vdd

Figure 1.2: NMOS LC-VCO

The NMOS structure in Figure 1.2a has the smallest sensitivity to noise on the ground level, however suffers from pushing, due to the high sensitivity to noise coming from power supply. On the other hand, this topology has a lower flicker noise, than those with current source to the supply represented in Figure 1.2b [3]. Moreover, as the inductors are con-nected to the supply voltage, both structures can achieve an output signal swing twice the power supply voltage. This feature can lead to a phase noise reduction, since noise is strongly dependent on the oscillation amplitude.

In the same way, the structures shown in Figure 1.2 can be implemented using PMOS transistor. Although for carrying the same current, and because PMOS are not as fast as NMOS, typically the width increases by a factor of 2-3 (consequently, large implementation area), they are less vulnerable to flicker noise as the Bulk terminal is connected to the source (assuming an ideal power source).

There is a possibility to combine NMOS and PMOS in the structure, taking advantage of the best performance of each one, obtaining the topology represented in Figure 1.3. This type of structure has as main advantage the reduction of the power consumption to half when compared to those in Figure 1.2. The choice about where to place the current source depends on whether our concern is to make to oscillator less sensitive to ground or to power supply levels. The circuits shown before share the basic concept of providing a negative resistance in opposition to that in the tank, so that the overall losses are reduced. Moreover, this negative resistance will also improve the “quality” of the oscillator, since the average power dissipated is reduced.

Finally, the architectures presented are fully integratable in CMOS technology device (reducing both the number of external components and connections and as result reducing the parasitic effects), and show a better phase noise performance [6].

Introduction

35

c) Current source to ground d) Current source to Vdd

Figure 1.3: Double switch LC-VCO

Although analog/RF design is not a new topic, the state of the art regarding analog considers [2]:

− There is no universal approach for analog design. The design methodology is usually based in designers experience and previous knowledge. Sometimes, the try-and-see design, supported by simulations, is still used.

− A large number of CAD tools are offered, mostly for simulation and layout generation of analog circuits.

− A considerable number of analog design automation tools have been proposed by Academia. However, these tools suffer from the lack of a common approach and de-sign methodology, and usually are not adopted by the industry. On the other hand, digital design automation tools are quite well accepted by designers.

As a result, and supporting the motivation for this work, there still exist a few number of issues that to be taken into account, and does not have an unanimous answer among de-signers, such as:

− As technology is scaling down, how to deal with both increasing complexity of ana-log/RF circuits, and the ever more stringent specification?

− Is it possible to design an analog/RF device, through optimization procedures, and still attaining to the best design trade-offs?

− Is it possible to transfer knowledge and personal know-how to the optimization tool?

Introduction

36

− Is it possible to shorten the design time for hand-calculations and elec-tric/electromagnetic simulations?

− Is there any benefit in going firstly through an optimization-based design and then to a final simulation, rather than to a full simulation-based design?

− How to give designers the possibility of being aware about device physics impact in circuit performance, and at the same time take them it into account in the design process?

− Is it preferable to have an accurate design based on blind believing simulators, rather than a less accurate design but in which it is possible to get a deep knowl-edge concerning the device behaviour?

These are just some of the questions that, probably, a designer holds in his mind.

Summarizing, the above issues highlight the trade-off between design accuracy and de-sign time. If, on one hand, the requirement to provide useful insight into circuit behaviour, si-multaneously with the necessity for circuit correction, makes prohibitive the use of numerical optimizers or fully automated CAD tools; on the other hand, analytical-based systems, usually, run faster, are able to deal with complex circuit design, and are easily adaptable to new “re-alities”, such as new technology processes, among others. In Figure 1.4, a qualitative com-parison between simulation-based and analytical-based design tools is depicted. With today’s electric/electromagnetic simulators, the effort to simulate a specific circuit mostly depends on the circuit design level, i.e., if it is a circuit description level or a physical description level. In the particular case of LC-VCO several hours may be needed to perform a single simulation. Analytical-based design tools are known for being fast in characterizing the circuit behaviour; however, generally, it takes a long time to setup.

SIMULATION-BASED

TOOLS

(“SPICE-in-the-loop”) ANALYTICAL-BASEDTOOLS

hour

day

week

month

year

hour day

week

mon

th

year

How long to setup?

How

long

to

run?

+ same setup as validation+ quicker to set up– slowest to run; scaleup?

+ run really fast !+ scale up to big things– long setup; accuracy?

Figure 1.4: Analog Design characteristics: simulation vs analytical tools

[source: Rob A. Rutenbar, “Analog Synthesis (and Verification) Revisited: What’s Missing?” Invited Ple-nary Talk at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Appli-cations to Circuit Design (SMACD), Seville, Spain, September 2012]

Introduction

37

1.2 Problem Formulation

When designers have in hands the task of designing a VCO, one of the main chal-lenges is to obtain results between simulation and on-chip measurement as close as possible. For this propose, it is essential to have accurate models for each of the circuit blocks.

As aforementioned a VCO should provide a signal within a certain frequency as pure as possible and which can be adjusted by external voltage. As can be seen in Figure 1.3 (sec-tion 1.1), a VCO has two main blocks; the LC tank responsible for the oscillation frequency, and the active circuit which is responsible for reducing the circuit losses introducing a negative resistance. Most of the LC-VCO designs have as main criteria to achieve both minimum phase noise and minimum power consumption for a certain oscillation frequency and desired tuning range. In a very simplistic point of view, for a specified frequency and tuning range (and maximum phase noise), the design problem to be worked out is the sizing of all the elements of the LC-VCO. As the correlation among the design variables is very strong, this has yielded in a large number of design methodologies has being proposed in the literature, as will be presented in chapter 2. Notwithstanding, a brief introduction can be offered at this point. The type of approach followed could be the key for the success of the design in achieving the best solution. In order to design a full LC-VCO, designers must take into ac-count the following components’ parameters:

− Inductance value, L, and its parasitics;

− Capacitor capacitance, C, and parasitic resistance;

− MOS transistor: characterisation, technology, parasitics, models, ...

Most of the bibliography focuses the design of the LC-VCO in the trade-off between phase noise and power consumption. The main issue focused, concerns the design of circuits with low current consumption without phase noise degradation.

In [7] a complete description of a design of integrated LC-VCOs is presented, where the complexity of the optimization design, regarding the number of variables involved, is fo-cused. The design of a fully on-chip LC-VCO requires simultaneous optimization of multiple variables, where the major difficulty is to estimate the losses on-chip, mainly due to the induc-tor, which gives to the on-chip circuit a worst performance than that obtained for an off-chip circuit. The use of computer-aided optimization is essential to find the optimum design in such a complex circuit. Although, this sometimes is understood as to limit the designers’ sensibility to the trade-offs among the parameters involved, as the result achieved is copiously reliant on optimization process. To overcome the mentioned drawback, a graphical optimization method-ology which uses graphical nonlinear programming (GNP) is proposed [7]. With GNP, de-signers have a 2D graphical visualization of the design constraints, which provides essential

Introduction

38

intuitions in finding the optimum solution. The optimization process can be summarized in three main steps as following:

− The tail current in the oscillator must be set to Imax. The drain current in each tran-sistor is the dominant contributor to the phase noise;

− The inductor inductance must be fixed, and an inductor that minimizes the losses should be chosen. The inductor is the element responsible for the most of the losses, so as higher the losses, smaller is the design space;

− For the selected inductor, the optimization process is evaluated taking into account the design constraints. If a practicable design point is achieved, a new optimization process is evaluated for a lower inductance value.

− This procedure is repeated until the design space (2D design space) is reduced to a single point, the optimum design.

The optimization methodology presented before, is just one from an extensive range of different methods adopted for the oscillator design that can be found in the literature. A few more examples will be briefly referred as following:

− In [8], Matlab, Cadence SpectreRF and ASITIC are used. Here, the LC-VCO design optimization is based on the gm/ID methodology, where the oscillator design space is studied with the goal of choosing the optimum design, considering phase noise – consumption trade-off;

− In [9] a graphical optimization method is presented. In this work, design constraints are imposed on tuning range, tank voltage amplitude, star-up condition, power con-sumption and phase noise. Those constraints are graphically represented in order to give to the designer an overview of the correlation between design parameters. The results obtained by analytic form are verified with simulation using ADS;

− In [10] for the design optimization a geometric programming method is used. The geometric program (GP) is a type of mathematical optimization problem character-ized by objective and constraint functions in a special form. Here, Matlab was used for solving the convex form of a GP. The design constraints mentioned in the previ-ous work, were also considered in this work.

As mentioned, the design and optimization process of and LC-VCO can be very di-verse. The type of application for the oscillator, CMOS technology used, models’ complexity … are just few of the points that make the design and optimization of a fully integrated LC-VCO one of the most challenging tasks.

Introduction

39

As a final remark regarding any LC-VCO optimization process is that it ought not to be seen as the final design, and subsequent simulation must be done in order to tune the design to comply with the desired specifications.

1.2.1 Research Question

This work aims to develop a tool to support the design of an LC-VCO oscillator. Under the umbrella of such a broad subject, the following sentence spotlights the research question of this work.

Would evolutionary algorithms be capable of improving the performance and achieve the best design solution of an LC-VCO optimization process, that ought to take into account accurate models of each component, as well as to be adaptable to technology changes and take into account technology/design constrains.

1.3 Contributions

This research has spotlighted the optimization based design of LC voltage controlled oscillators, by means of evolutionary algorithms. Such design involves some design trade-offs and relies on the estimation of several correlated parameters, consequently, traditional hand-calculation methods are not an option when CMOS submicrometer technology is being used. On the other hand, simulation based optimization, which is generally the most accurate design procedure, usually is an extremely time consuming process and can become prohibitive if fast design, or at least a fast first design approach, is desired.

To achieve the goal proposed for this thesis, the early chapters emphasis is placed on finding the most suitable analytical models that characterize with good accuracy the behaviour of each single element in the circuit: the CMOS transistor, the inductor and the varactor. These models, which must rely on technological parameters, in opposition to those based in fitting parameters supported by an exhaustive simulation process, are a fundamental key for an optimization based design procedure, that aims to be simulation independent. Such kind of analytical models, allows to understand the device physics and to apply it successfully for the analog/RF design purposes.

In the later chapters the focus goes to the optimization procedure based on evolutionary algorithms, namely the genetic algorithms. Due to the different kind of nature of the problem under analysis, which can be discrete, continuous, non-differentiable, or even mixed search spaces, genetic algorithms were chosen. Moreover, this optimization technique help designers dealing with design trade-offs, such as phase noise and power consumption, in an intuitive way, avoiding the blind believe in simulators.

Introduction

40

As a final remark, it will be shown that the performance of the LC voltage controlled oscillator, designed by the proposed optimization-based design tool, gives fairly acceptable results when compared with those obtained through commercial simulators. It proves that the proposed tool is a good design instrument for a first approach design, as intended to be.

The following book chapters, journal and conference publications have resulted from the work presented in this thesis:

• Pereira, P., H. Fino, F. Coito, and M. Ventim-Neves, "ADISI- An efficient tool for

the automatic design of integrated spiral inductors", IEEE International Confer-ence on Electronics, Circuits, and Systems (ICECS), pp. 799–802, December, 2009.

This work introduces a tool for the optimization of CMOS integrated spiral inductors. The core of the tool is an optimization-based methodology where technology constraints on the inductor layout parameters are considered by applying user-defined discretization on the design variables. This is particularly important since it enables the generation of the best solu-tion for the technology used. Further constraints imposing predefined relation between layout parameters are also considered as a way of implementing heuristic design rules. The trade-off

between quality factor and device area is evaluated through the generation of a graphical rep-resentation of quality factor versus output diameter for a given inductance. For the sake of simplicity the π-model has been used for characterising the inductor. The validity of the design results obtained is checked against circuit simulation with ASITIC. The main limitation of the work proposed resides in the applicability of the tool to higher frequencies. This limitation is inherent to the π-model used for the integrated inductor, which is valid for frequencies lower than 1GHz.

• Pereira, P., M. H. Fino, and F. V. Coito, "Using discrete-variable optimization for CMOS spiral inductor design", International Conference on Microelectronics (ICM), pp. 324–327, December, 2009.

In this paper a discrete-variable optimization methodology for the automatic design of CMOS integrated spiral inductors is proposed. The use of discrete variable optimization proce-dure offers the designer the possibility for exploring the design space exclusively in those points available for the technology under use. A comparison between using discrete-variable optimization and a continuous optimization procedure followed by a discretization of the results is presented, where the benefits of the proposed methodology are presented. In all examples the discrete–variable optimization proved to be better.

• Pereira, P., M. Fino, F. Coito, and M. Ventim-Neves, "GADISI – Genetic Algo-rithms Applied to the Automatic Design of Integrated Spiral Inductors", Doctoral

Introduction

41

Conference on Computing, Electrical and Industrial Systems (DoCEIS), pp. 515-522, February, 2010.

The main objective of the optimization based tool presented in this work, is to generate the geometrical layout parameters of integrated spiral inductors. For this purpose two main concerns were considered. On one hand, a Genetic Algorithm (GA) optimization procedure where a technology-aware methodology is adopted, and the discrete nature of the variables is also accounted for as a way of restricting the search space to those points allowed by the technology. Furthermore, GAs do not require derivative information or previous knowledge, as well as the algorithm determines global optimum solutions, avoiding getting trapped in local maximum/minimum, as frequently happen with continuous variable optimization algorithms. On the other hand the necessity for obtaining solutions in an efficient way led to the use of the inductor physical model, instead of using a simulation based approach. The Matlab GA tool-box is used, and some GA functions were added, yielding technology feasible solutions is presented. For the sake of efficiency and simplicity the π-model is used for characterizing the inductor.

• Pereira, P., M. H. Fino, and M. Ventim-Neves, "Automatic generation of RF inte-

grated inductors analytical characterization", International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD), pp. 1-4, October, 2010.

This paper addresses the automatic generation of RF integrated inductors model for wider frequency range. In this work the double π-model is used as a way of characterizing the inductor behaviour for frequencies above the 1.0 GHz. The double π-model is supported by a set of equations based exclusively in technology parameters instead of equations obtained by fitting process of measure data. The main advantages of the tool presented in this work when compared to using an electromagnetic simulator reside not only in the computation time but also in the possibility for being fully integrated into an optimization based design tool. The use of a technology-based methodology for the evaluation of the model parameters grants the adaptability of the models generated to any technology.

• Pereira, P., M. Helena Fino, F. Coito, and M. Ventim-Neves, "RF integrated in-ductor modeling and its application to optimization-based design", Analog Inte-grated Circuits and Signal Processing, vol. 73, issue 1: Springer Netherlands, pp. 47-55, 2011.

In this work an optimization-based approach for the design of RF integrated inductors is addressed. For the characterisation of the inductor behaviour the double π-model is used. The use of this model is twofold. On one hand it enables the generation of the inductor characteri-sation in a few seconds. On the other hand its integration into the optimization procedure is

Introduction

42

straightforward. The inductor analytical characterization is integrated into an optimization-based tool for the automatic design of RF integrated inductors. This tool uses a Modified Genetic Algorithm (MGA) optimization procedure, where user defined constraints on the design pa-rameters are taken into account. This tool allows overcoming the typical limitation of most non-commercial tools, such as ASITIC, regarding their impossibility for being integrated into an optimization loop.

• Pereira, P., H. Fino, F. Coito, and M. Ventim-Neves, "Optimization-Based Design

of Nano-CMOS LC-VCOs", Doctoral Conference on Computing, Electrical and In-dustrial Systems (DoCEIS), pp. 453-464, February, 2012.

This paper introduces a variability-aware methodology for the design of LC-VCOs in Nano-CMOS technologies. The complexity of the design as well as the necessity for having an environment offering the possibility for exploring design trade-offs has led to the develop-ment of design methodologies based multi-objective optimization procedures yielding the gen-eration of Pareto-optimal surfaces. The efficiency of the process is granted by using analytical models for both passive and active devices. Although physics-based analytical expressions have been proposed for the evaluation of the lumped elements, the variability of the process parameters is usually ignored due to the difficulty to formalize it into an optimization perform-ance index. The usually adopted methodology of considering only optimum solutions for the Pareto surface, may lead to pruning quasi-optimal solutions that may prove to be better, should their sensitivity to process parameter variation be accounted for. In this work we pro-pose starting by generating an extended Pareto surface where both optimum and quasi-optimum solutions are considered. Finally information on the sensitivity to process parameter variations, is used for electing the best design solution.

• Pereira, P., H. Fino, and M. Ventim-Neves, "RF Varactor Design Based on Evo-lutionary Algorithms", International Conference on Mixed Design of Integrated Cir-cuits and Systems (MIXDES), pp. 277-282, May, 2012.

This paper introduces an optimization methodology for the design of RF varactors. The characterization of the varactor behaviour is supported by a set of equations based on techno-logical parameters, granting the accuracy of the results, as well as the adaptability of the model to any technology. The varactor design is achieved through the implementation of a Genetic Algorithms (GA) optimization methodology, which is able to deal with continuous and/or discrete variables, making possible to suit both technological and layout constraints. The results presented, spotlight the potential of varactor analytical model, combined with a GA optimization procedure, when integrated in optimization design tools.

Introduction

43

• Pereira, P., A. Sallem, M. Fakhfakh, M. H. Fino, and F. Coito, "A Technology-Aware Optimization of RF Integrated Inductors", Analog Circuits: Applications, Design and Performance: Nova Science Publishers, Inc., pp. 213-234, February, 2012.

This book chapter presented the optimal design of RF integrated spiral inductors, through the use of Particle Swarm Optimization (PSO), as an alternative to genetic algorithms optimization. The efficiency of the design process is granted by using an analytical model to characterize integrated inductors based on the double π-model. Physically-based equations for the evaluation of the model parameters are considered, as a way of easily adopting the model to any new technology. PSO is used to generate optimal values of parameters of the devel-oped models. Several working examples for mono-objective and multi-objective optimization were considered. The viability of the obtained design solutions is highlighted via comparison with ASITIC simulation results.

• Coito, F., H. Fino, and P. Pereira, "Variability-Aware Optimization of RF Inte-

grated Inductors in Nanometer-Scale Technologies", Integrated Circuits for Analog Signal Processing, New York, Springer-Verlag, pp. 271-288, 2012.

A multi-objective optimization based methodology for the design of integrated inductors is addressed in this book chapter. The necessity for obtaining design solutions robust against the technological parameters variability has led to a new methodology where an extended-Pareto surface is generated. This extended-Pareto front contains both optima solutions and quasi-optimum solutions. Finally information on the robustness against process parameter variations is used for electing the best design solutions.

• Pereira, P., H. Fino, and M. Ventim-Neves, "LC-VCO design methodology based

on evolutionary algorithms", International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), pp. 189-192, September, 2012.

This paper introduces an LC-VCO design methodology based on evolutionary algo-rithms. The oscillator analytical model is supported by a set of equations based exclusively in technology parameters. The optimization design tool presented in this work has two main ad-vantages: i) as the VCO model is based in technological parameters, it may be straightfor-wardly adapted to new technologies; ii) reduced computation time, if compared with electro-magnetic simulator-based optimization procedure. A set of working examples for UMC130 technology, aiming the VCO phase noise and power consumption optimization, is addressed. The results presented, spotlight the potential of the proposed design methodology, combined with a GA optimization procedure, for an accurate and timely efficient oscillator design.

Introduction

44

• Pereira, P., M. Helena Fino, and M. Ventim-Neves, [Invited article based on "LC-VCO Design Methodology Based on Evolutionary Algorithms" – SMACD 2012], Analog Integrated Circuits and Signal Processing, Springer Netherlands, pp., 2013. – To be published

This article is an extended document based on the previous work, where a more de-tailed explanation regarding the LC-VCO design methodology based on evolutionary algo-rithms, is offered.

• P. Pereira, H. Fino, M. Fakhfakh, F. Coito, M. Ventim-Neves, "LC-VCO Design

Challenges in the Nano-Era", Analog/RF and Mixed-Signal Circuit Systematic Design, vol. 233, Springer Berlin Heidelberg, pp. 363-379, 2013.

This book chapter, put together some of the previous publications, and gives a full overview regarding the complexity of designing LC-VCOs, which has lead to the development of several design methodologies. The design of LC-VCO is supported by a Genetic Algorithms optimization methodology, which is able to deal with both continuous and discrete variables, making possible to satisfy both technological and layout constraints, proposed in early works, is presented in this chapter. A set of design examples showing the design of three VCOs for different oscillation frequencies were considered. The feasibility of the obtained design solu-tions is highlighted via comparison with simulated results.

1.3.1 Other Related Publications

In parallel with the present work, a few other publications regarding similar lines of re-search were also possible due to a fruitful collaboration with their co-authors.

• Pereira, P., F. Coito, and H. Fino, "PSO-Based Design of RF Integrated Induc-tor", Doctoral Conference on Computing, Electrical and Industrial Systems (Do-CEIS, pp. 475-482, February, 2012.

• Sallem, A., P. Pereira, M. Fakhfakh, and H. Fino, "A Multi-objective Simulation Based Tool: Application to the Design of High Performance LC-VCOs", Techno-logical Innovation for the Internet of Things, vol. 394, Portugal, Springer Berlin Heidelberg, pp. 459-468, 2013.

• P. Pereira, M. Kotti, H. Fino and M. Fakhfakh, “Metaheuristic Algorithms Compa-raison for the LC-Voltage Controlled Oscillators Optimal Design”, The 4th IEEE TN CEDA’s ENG-OPTIM’ Contest: ‘‘Engineering Applications of Optimization Techniques’’, pp., April 2013 – To be published

Introduction

45

1.4 Chapter by Chapter Overview

The remainder of the thesis is organized as follows: Chapter 2 describes in more detail the background of the work developed, in particular the analog/RF design methodology and strategy applied to LC voltage controlled oscillators. A special attention will be given to ana-log/RF design tools based in analytical models, instead of simulation-based design tools. Chapter 3 introduces the EKV MOS transistor model as the path for the accurate characteri-zation of the transistor behaviour. The CMOS transistor has been widely used, not only as an active element, but also as a passive device, in the figure of a varactor. Chapter 4 presents the planar spiral inductor. Moreover, accurate and technological dependent analytical models are identified, aiming its inclusion in an optimization-based design procedure. The optimal de-sign of radio-frequency integrated spiral inductors and capacitors, supported by means of evo-lutionary algorithms, is presented in Chapter 5, while Chapter 6 addresses the optimal design of a full LC voltage controlled oscillator, taking into consideration circuit specifications and de-sign trade-offs. Finally the overall conclusions and suggestions for future work are presented in Chapter 7.

47

2 Background on VCO Design and Optimization Methodologies

In this chapter the background information necessary for the understanding of several key aspects regarding the design and optimization methodologies of LC-oscillator circuits is addressed. Firstly, a general overview concerning the design of analog/RF circuits is pre-sented. Afterwards, a more detailed analysis is devoted to the techniques adopted by different authors, aiming the full design of an LC voltage controlled oscillator.

2.1 Introduction

Analog/RF design still is a knowledge-based design. Somehow, analog/RF design is based partially in the designer’s knowledge, a portion of designer’s intuition, the designer qualitative analysis, and suffers from the lack of design formalism. Even though, in a certain part of the design process, there is place for a formal mathematical approach, the analog/RF design can be contrasted with its counterpart, the digital design, in terms of design process, whereas digital design has, usually, straightforward design techniques.

It is usual to say that analog/RF design is more a form of art and less science. Since it relies in an intensive knowledge, is a multiphase and iterative task, and, consequently, it goes for a substantial period of time [11]. The absence of an analog/RF circuit design for-malism stems from the nonexistence of a circuit-independent design procedure and the lack of a formal representation, which allows a proper formalization of the problem. The nature of the analog signals that the device deals with, as well as it time dependency, is considered to be the main cause for the difficulty in achieving a structured problem representation. In the bibli-ography, the proposed techniques needed to produce successful analog/RF devices are gen-erally based in the experience, the know-how and skills of a small number of designers.

Background on VCO Design and Optimization Methodologies

48

Notwithstanding, analog/RF design tools can provide initial candidate solutions, which can be seen as a starting point for a final design. In the last decade, there have been a ‘boom’ in analog tools, aiming to help designers in obtaining an accurate design, providing an initial and fairly precise solution that can be applied to formal tools, e.g. electromagnetic simu-lators. The nature of continuous signals domain in analog circuits, requiring the application of calculus, is in general costly in terms of complexity. Yet, the problem can be simplified if con-verted to a discrete problem domain, which is liable to be included in a logical structured problem, offering an approximation to a final design solution. These issues, allied to the de-mand for smaller device sizes and higher scales of integration, climbs up a few steps in circuit design complexity.

Generally, the accuracy to which analog/RF design are devoted to, simultaneously with the rising need for analog/RF system simulation, makes the design time for analog/RF cir-cuits the bottleneck of any analog design. Even though 90% of an integrated circuit may pos-sibly be digital and only 10% reserved for analog, most of the design time and endeavour is dedicated to the analog part [11]. Moreover, the design of digital circuits is rather fairly sup-ported by computer-aided design tools than its analog counterpart. In Figure 2.1, a qualitative comparison between digital and analog design is depicted.

DESIGN

TOOLS

Design Effort(& Complexity)

Design Effort

(& Complexity)

DESIGNTOOLS

DIGITAL ANALOG

Des

ign

Pro

blem

(%)

Figure 2.1: Digital vs analog design

The LC voltage controlled oscillator, as a pure analog circuit, suffers from the same ad-vantages and drawbacks regarding its design problem formulation, as abovementioned. As result, many have tried to develop analog tools for the design, layout and characterization of LC-VCOs, aiming to help analog designers in their effort in achieving the best circuit perform-ance, compliant with circuit’s specifications.


49

2.2 Early Work

The design of LC voltage controlled oscillators implies several different aspects, which allows saying that it has a long history back to early researches, such as Maxwell, whose laws are applied to magnetic effects.

In recent times, the design and optimization of LC oscillators by means of geometric program was proposed in [12]. The authors stated that the synthesis method is fast, and global optimization design is determined, where the final solution is completely independent of the starting point. The optimization process through geometric program is very efficient, ac-cording to the authors, allowing designer to spend more time exploring design trade-offs rather than sizing the circuit elements, where the design methodology engage twelve variables. From our point of view, the weakest points of the work proposed in [12], are, specially, the analyti-cal models used for the circuit elements characterization. For the inductor characterization Greenhouse’s approach is used, however the model adopted suffers from the lack of accuracy at high frequencies, above 1GHz, whereas for the varactor an ideal capacitor in series with a resistor is considered. A couple of design examples in a standard 0.35µm, 2.5V CMOS proc-ess, where the optimization algorithm deals with a single objective function, the minimization of the oscillator phase noise, are offered. Despite good performance achieved, results valida-tion, at least, against device-level simulations is not presented.

An automated and layout-aware RF LC-VCO design, entitled CYCLONE was offered in [13]. The proposed tool combines in the design process both the device-level simulation for granting the accuracy of the tool and the advantage of evolutionary algorithms, respectively the simulated annealing algorithm, for the search of the best feasible solution. As a tremen-dous effort is put on the design accuracy, electromagnetic finite-element simulators are used, in particular for the inductor characterization, as its parasitics can easily jeopardize expected performances. In CYCLONE, two electromagnetic simulators are used, increasing the design process complexity. As result, the design time of the LC-VCO is mainly engrossed by simula-tions. A few design and layout generation examples for two VCO topologies are shown. A low resistive substrate 0.35µm, 1.8V CMOS process was used.

A design strategy focused in the inductance selection scheme is performed using a graphical optimization method to optimize the phase noise of a cross-coupled LC-VCO, sub-jected to design constraints is presented in [14]. The main idea is to obtain graphically a search space, called feasible design regions, based on circuit specifications, as well as design constraints, and then to look forward for the best design solution. The advantage of the method is that it provides physical insight into the space search, allowing designers to adjust the design solution according to their knowledge and experience, which can be seen as a negative aspect. On the other hand, as the highlight was put in the graphical optimization side, the varactor and transistor analytical models are supported by several approximations,


50

which bring some inaccuracy to the final design. The LC-VCO design examples shown were obtained n a 0.35µm, 2.5V CMOS process.

The design of a cross-coupled LC oscillator in a 0.25µm, 2.5V CMOS process, achiev-ing low phase noise with low power consumption and wide tuning range is addressed in [15]. In this work the VCO design methodology is not sustained in computer-aided design tools, but supported in the expertise and intuition of the designers. Yet, the authors provide important information regarding design trade-offs, which are very helpful for being integrated in an opti-mization-based design methodology.

An LC-VCO design and optimization example is shown in [7], where 12 independent design variables were identified; 4 of them regarding to the transistor dimensions, other 4 re-lated to the geometric parameters of the integrated inductor (metal width, metal space, num-ber of turns, and external diameter), 2 associated to the varactor (maximum and minimum capacitance), the load capacitance, and finally the tail current in the oscillator. A design ex-ample of the design of an LC-VCO for a specified set of specifications (centre frequency, tun-ing range, …) and having the phase noise as the objective function, is shown. As a design strategy, aiming to reduce the complexity of the optimization process and, consequently the number of variables, only the dominant sources of noise were considered on the phase noise function, yielding a reduction of 50% on the number of independent variables. The 6 inde-pendent design variables to optimize are: transistors width, varactor maximum capacitance metal space, number of turns, and external diameter from the inductor, and the tail current in the oscillator. For the optimization design methodology a graphical nonlinear programming (GNP) is proposed. The use of such methodology can be seen as an intuition-optimization methodology, since the final design step relies on the designer skills.

A lot of researchers pay attention at phase noise analysis, as well as the different noise sources, when designing an LC-VCO, since it plays an important role in circuit performance. A numerical optimization technique based on analytical equations applied to the design of a cross-coupled differential CMOS LC oscillator is addressed in [16]. According to the authors, to take the advantage of Leeson’s equations for estimating the circuit phase noise, an optimi-zation routine was built, using sequential quadratic programming (SQP), which is generally applied for nonlinear optimization problems. As a strong drawback, this work considers a very simplified tank model, reducing the complexity of the optimization process at the expense of the results accuracy.

Considerable research efforts have been devoted to achieve low phase at minimal power consumption. Different techniques applied to each component of the LC oscillator, such as improving the tank quality factor, noise filtering techniques, or manipulating the device size are proposed in [17] and [18]. Integrating these techniques into an oscillator design aiming to reduce phase noise, relies on the assumption that large output swing is achieve, thus caus-


51

ing high current consumption, increasing power consumption. In [19] an alternative approach, where an optimal trade-off between thermal-noise-induced phase noise and DC power dissi-pation can be obtained if the active elements of the circuit, the transistors, were designed to operate at the boundary between saturation and triode regions. This technique was applied to the design of a 2 GHz LC-VCO, implemented in a standard 0.18µm, 1.8V CMOS process. Still, in the domain of oscillators design based on phase noise (PN) techniques, in [20] is proposed a time dependent PN model implemented in VHDL-AMS language.

In [21], a demonstration of the feasibility of gathering injection-locked frequency divid-ers with an LC-VCO, taking advantage of the oscillator low phase noise at high frequencies, mainly due to higher Q achieved by inductors, and achieving better phase noise in a wide range of operating frequencies by using a multiple frequency divider technique is presented. With such architecture, the improvement in phase noise characteristic is obtained at the cost of larger power consumption of the VCO.

A computer-aided optimization technique using geometric programming (GP) for the de-sign of CMOS LC-VCO circuits was used in [10]. The analog circuits under analysis con-verted to GP language, combined with the technological process data, also converted to GP language, are incorporated into Matlab GP solver that determines the size of all the circuit elements. Also in this work, as the goal is the proof of concept of the optimization methodol-ogy proposed, the analytical models of each element use in the design process are very sim-ple, not taking into account many of the parasitic effects involved, neglecting its effect on cir-cuit performance. The design of a cross-coupled LC-VCO for an operating frequency of 2.5 GHz, in a standard 0.35µm CMOS process, is addressed. In [9], the same authors go one step ahead and adopted a graphical optimization methodology, based in their previous work. They claim as main improvement the possibility of having an overview of the correlation be-tween design parameters, in order to gain an understanding, or gain sensitivity, for the behav-iour of the circuit. The results obtained by analytic form, for a 4.0 GHz oscillator in a standard 0.35µm CMOS process, are verified against simulations through Advanced Design System (ADS).

The LC-VCO design optimization based on the gm/ID methodology, where the oscillator design space is studied with the goal of choosing the optimum design, considering phase noise - consumption trade-off is presented in [8]. For the phase noise estimation the Linear Time Variant (LVT) approach is used. The gm/ID is a universal characteristic curve, specially used for long channel MOS transistors. Although, when short channel effects turn out to be significant, this curve depends slightly on transistor size, its mobility, among other parameters of the particular technology used. This means that to obtain an accurate gm/ID fitting function, dependent only on the MOS transistor dimensions, electric simulations are needed. In this work, and depending on the circuit application and technology process, two ways of acquiring


52

the gm/ID curves are considered. In a simple way, for long channel devices analytical compact models, such as ACM [22] or EKV [23] are used. These models allows to obtain the gm/ID curve, simply by fitting the slope factor n with data previously obtained by measurements or by simulations. Whereas, when short channel devices effects cannot be neglected, electrical simulations are used to obtain the gm/ID curve. An iterative optimization routine was imple-mented in Matlab, where combining the relationships between (gm/ID, Lind) vs ID, (gm/ID, Lind) vs phase noise and (gm/ID, Lind) vs varactor capacitance, is used to obtain a final design. From our point of view, the main drawback of the proposed tool is it dependence on electric and electromagnetic simulators. For instance, inductor parasitics are obtained through ASITIC simulations, and final simulations are performed with Cadence SpectreRF. Two different LC-VCO designs, for two different technological CMOS process, in the region of 1 GHz (0.35µm, 3.0V) and 2.4 GHz (90nm, 1.2V) respectively, are offered.

More recently, an alternative approach to the LC oscillator design is proposed in [24]. As already seen, the trade-off between phase noise and power consumption is the driving force in the design process. As a way to encapsulate these two objective functions, the so called figure of merit (FoM) is adopted. The FoM traduces the performance of a specific cir-cuit, relatively to its phase noise and consumption. However, it does not mean that the lowest phase noise is obtained, neither minimal power consumption is achieved. It is usually seen as a metric for circuit performance comparisons. In this work, the design optimization methodol-ogy is supported by differential evolution (DE) algorithm. DE is a metaheuristic method that optimizes a problem by iteratively trying to improve a candidate solution with regard to a given measure of quality, in this work, the FOM. This type of optimization approach is quite suitable for problems having more than one objective function and design constrains, which adds more complexity. The lack of information regarding the accuracy of the passive and active elements analytical model is the major bottleneck of the proposed tool. Although, a design example of an LC-VCO working at a frequency of 2.5 GHz, implemented in a 90nm CMOS technology, 1.8V, showing reasonable accordance with Cadence Spectre ADE simulation, is shown.

A similar LC-VCO design approach, which takes under consideration trade-offs between power consumption, phase noise and tuning range encapsulate in a single cost function, by means of the FoM, is presented in [25]. The proposed tool aims to be technology independ-ent, but at costs of design libraries previously obtained, which consists of devices templates and circuits schematics. Moreover, during the design process, simulations are performed in order to obtain the sizes of some components, which are crucial in circuit performance such as the capacitor. In this work, two different LC-VCO designs, for different technological CMOS process (0.13µm and 90nm, 1.2V), for an oscillation frequency of 2.4 GHz, are presented.

A general overview of an LC-oscillator optimization-based design, gathered through the analysis to previous work in the subject, is depicted in Figure 2.2.


53

Figure 2.2: General overview of an optimization-based design

As it is possible to observe, throughout the several LC-oscillators design and optimiza-tion methodologies presented before, there is an nonexistence of a clear and well defined de-sign strategy, instead, each designer has its own approach to the problem under analysis, and generally their knowledge and skills are a key factor for a successful design. In Figure 2.3, a chronological map summarizing the different MOS technology process adopted in the several works detailed analyzed in this chapter is presented. Most of the works offered as working examples of their design/optimization methodology, the design of a LC-oscillator for an oper-ating frequency around 2.4 GHz, since this is typically a band for RF device communications, and broadly used.

2009

2007

2005

2003

2001

1999 2011

Tech

nolog

y Pr

oces

s

Figure 2.3: Chronological map regarding the State-of-the-art of LC-oscillators design


54

Most of the works that have been published uses different MOS technology processes, which goes from 350 to 90 nm. Concerning the oscillator working frequency, as nearly all works propose circuits for RF applications, its oscillation frequency is set between 1.8 and 2.4 GHz. There is one oscillator characteristic that shows to be quite unchangeable over the dif-ferent technology processes and frequency, which is the phase noise. As can be seen in Ta-ble 2.1, the phase noise only varies around 5% for a given offset frequency. Identical obser-vation is also valid for the oscillator figure of merit.

Table 2.1: Published VCO’s characteristics

Ref. Tech.

Process Freq. [GHz]

Id [mA]

Vdd

[V] ∆ f

[MHz] L(∆ f)

[dBc/Hz] FoM [dB]

[12] 350 nm 1.8 5.0 2.5 0.6 -124.2 -

[12] 350 nm 1.8 1.6 2.5 0.6 -118.5 -

[13] 350 nm 3.0 11.0 1.8 0.6 -115.0 -

[14] 350 nm 2.0 4.0 2.5 0.6 -117.0 -

[15] 250 nm 2.4 4.5 2.5 0.5 -116.0 -

[7] 350 nm 2.0 4.0 2.5 0.6 -117.0 -

[16] 250 nm 2.4 5.0 2.5 1.0 -124.0 -

[19] 180 nm 2.0 2.7 1.8 0.1

2.0

-103.0

-125.0

182

-

[21] 90 nm 3.0 - - 1.0 -126.0 190

[10] 350 nm 2.5 4.5 2.5 1.0 -120.0 -

[9] 350 nm 4.0 4.6 2.5 1.0 -126.0 -

[8] 350 nm 0.915 3.0 3.0 0.6 -121.0 -

[8] 90 nm 2.4 0.40 1.2 0.4 -107.5 -

[24] 90 nm 2.4 0.28 1.8 1.0 -119.7 190

[25] 90 nm 2.4 0.47 1.2 1.0 -116.8 187

[25] 130 nm 2.4 0.52 1.2 1.0 -117.1 187

2.3 Conclusions

This chapter presented background information on design and optimization methodolo-gies aiming a full automated design of an LC voltage controlled oscillator.

The research on analog simulators as well as on semi-automated CAD tools has been making notorious improvements, reducing traditional analog design bottlenecks. Yet, there are some design aspects that still divide designers, e.g. the trade-off between design time and


55

design accuracy. The necessity for circuit correction, mainly if an analytical-based design is firstly performed, and sometimes, simultaneously with the need of having useful insight into the circuit behaviour, can be seen as a design weakness. For few authors, there is no advan-tage in the use of numerical optimizers or fully automated computer-aided design tools. On the other hand, analog/RF tools are fundamental, at least, for a first design approach, avoid-ing unfeasible design solution. Afterwards, the designer experience and knowledge are valu-able skills for a final circuit design tuning.

57

3 CMOS Transistor Model

This chapter will present the EKV MOS Transistor Model and points out the advantages of its application for the characterization of the transistor current behaviour in analog/RF ap-plications. Furthermore, its application to the estimation of the transistor capacitances when used as a capacitor will also be addressed. Additionally, the extraction process of the EKV model parameters is offered, where its independency regarding empirical variables, usually obtained through fitting processes based in measured data, is highlighted.

3.1 Introduction

In any analog circuit design, such as in an LC voltage controlled oscillator, the design at the transistor level is one of the most critical aspects when using deep submicron technolo-gies. Traditionally, such design is mainly supported on designers’ expertise, since analog/RF circuit design suffers from the lack of universally defined design formalism, yielding a gap that should be overcome. This issue becomes even more important when trying to develop an automatic tool for the design of analog/RF circuits. In Chapter 2, the absence of a general analog/RF design strategy as clearly demonstrated, which combined with poor device models, yields to an inefficient design process. This leads to the need of an accurate transistor ana-lytical model, in order to characterize the transistor behaviour with enough reliability. Several authors have tried to define what a good transistor model is [26], [27], [28], [29], [30]. Since it is the right path for a successful design task, the main device model characteristics for analog design are summarised in [2]:

− The model should be based on physical behaviour, accounting for significant physical effects, such as mobility, velocity saturation, short/narrow channel effects.

− The model should be global, compact, accurate and with the smallest number of fit-ting parameters.

CMOS Transistor Model

58

− It should cover all geometry ranges of interest, as well as those that are not in-cluded during the parameter extraction procedure.

− Finally, accurate prediction of transistor behaviour in weak and moderate inversion regions is mandatory.

From a wide variety of MOS models there are a few that have shown good perform-ance when modelling the transistor behaviour in deep submicron technologies. The so called “spice models”, were created to be included in one the most well known circuit simulators, SPICE, developed by Berkeley University [31]. Despite the physical meaning of all model pa-rameters, it shows inexactness for submicron technologies and does not present a continuous characteristic among all transistor operating regions. The next generation of transistor models, also proposed by Berkeley University, were the BSIM models [32], [33]. These new models overcome the above mentioned Spice models limitations, presenting adequate accurateness in the transistor current characteristics for all transistor operating modes. However the huge number of variables, more than forty depending of the model version, makes this model more suitable to be included in an electric simulator than in hand-calculation design methodology, or to be integrated in dedicated tools for optimization based design. In Ecole Polytechnique Fédérale de Lausanne (EPFL), a new transistor model was proposed, named EKV. It was developed by C. Enz, F. Krummenacher and E. Vittoz (hence the initials EKV) around 1995 [34]. The most recent versions, version 2.6 and after, are dedicated to the design of low voltage and low power analog circuits implemented in submicron CMOS technologies [23]. The main advantages of the EKV transistor model, are the small number of parameters, much less than Spice or BSIM models, its compactness and the continuity of the model that shows fair accuracy in relation to transistor behaviour from weak to strong inversion regions.

The design of analog circuits is typically started by a hand-calculation method or through automatic dedicated design tools that mimic the designer methodology, then simula-tors are used to check the validity of results obtained. So, a good MOS transistor model that accurately characterizes the device behaviour, with a reasonable number of parameters and that models all significant physical aspects, is of superior interest for analog circuit design. The EKV MOS transistor model encapsulates all this features, which makes it one of the most used nowadays, either in analog/RF or digital circuits [3].

The popularity and scaling down of CMOS technologies resulted in its low cost and opened a door for the design of full on-chip device’. That means that MOS Technology is not only limited to transistors working as amplifiers, but also new applications for MOS transistors come up, such as capacitors, or being more specifically, it application as variable capacitors. The interest in a fully integrated LC voltage controlled oscillator for RF systems has increased in the last decade, and a relevant number of publications have been published [3], [35].


59

In this chapter, besides an introduction to the EKV MOS transistor model, the method-ology for the model parameters extraction is presented. Finally its applicability to characterize the behaviour of variable capacitors’ is addressed.

3.2 EKV MOS Transistor Model

The EKV MOS transistor model has been developed to yield the compact modelling and simulation of low voltage devices for application in low power semiconductor technologies. The main advantage of using the EKV model in the characterization of the MOS transistor behav-iour relies on the fact that a single accurate expression, valid from weak to strong inversion and from linear to saturation region, is used [36]. This characteristic makes the EKV model suitable for analytical design and simulation of analog circuits, allowing a deep insight into the device behaviour. The EKV model has been derived considering the charges in the transistor as a function of each terminal voltage,

BulkDraind

BulkSources

BulkGateg

VVVVVV

VVV

−=−=

−=

(3.1)

where Vg, Vs, Vd are the transistor gate, source and drain voltage referred to bulk [34],[37]. Although the model has been derived considering the charges in the transistor, an expression for the drain/source current, Ids, is proposed, where

( )rfsds iiII −= (3.2)

with Is, if, ir are the specific, forward and reverse current respectively, and given by

( )( )

2

2exp1ln

−+=

T

dsPrf U

VVi (3.3)

'02

12

PTs V

nUIΘ+

=β

(3.4)

given that UT is the thermal voltage, β0 is a transconductance parameter and n is the slope factor. The charges mobility reduction is taken into account by the mobility reduction coeffi-

cient Θ and 'PV which is dependent on the pinch-off voltage, PV .

( )22' 221

TPPP UVVV ++= (3.5)

TP UVn

421

+++=

φγ

(3.6)


60

−

+−−=

22

'2'''' γγγφ ggP VVV

(3.7)

where 'gV is the effective gate voltage, γ

is the body effect parameter, 'γ is the corrected

body effect parameter taking into account the device geometry, and φ the bulk Fermi potential.

φγφ ++−= togg VVV ' (3.8)

+

−++−= s

effeffd

effox

ro VWWETA

LLETAV

LLETA

Cφφ

εεγγ 3'

(3.9)

Given that Vto is the threshold voltage for VSB = 0 V, εo is the permittivity of free space, εsi is the permittivity of silicon, Cox is the gate-oxide capacitance per unit area, Leff and Weff are the transistor effective length and width respectively. Finally, LETA and WETA are the short chan-nel and narrow width effect coefficients.

The next subsection will focus on the EKV DC parameters extraction process, giving a clear idea on how to perform it.

3.2.1 EKV Model Parameters Extraction

Although, the analysis and results presented in this section consider an NMOS transis-tor, a similar methodology is perfectly valid for PMOS transistors. The EKV model parameters extraction procedure is illustrated in the flowchart of Figure 3.1. The parameters extraction procedure was based on transistor characteristics obtained through simulations with HSPICE software and considering the UMC130 technology, as real measurement data were not avail-able. For this procedure the BSIM model L130E_HS12_V241 valid for RF NMOS transistors was adopted.

The very first step on extracting the EKV DC model parameters, is the determination of the specific current, Is, as this information is crucial to correctly determine all regions of opera-tion, as well as to obtain the pinch-off voltage characteristic, VP = f(Vg) [2]. Considering a MOS transistor operating in strong inversion, the reverse current, Ir, can be neglected and the current Ids may be given by:

( )224 sPT

sds VV

UII −=

(3.10)

thus,

slopeUI

VI

T

s

s

ds =−=∂

∂2

(3.11)


61

BSIM libTransistor W&L

Other tech param

Initial calculationsOxide capacitance, Cox

Body effect parameter, γBulk fermi potential, φ

Get IS Write .sp file Hspice simulation:Id = f(VG,VS)

FittingOutputIS and Id for all VG

Get VPWrite .sp file Hspice simulation:

VP = f(VG,VS)

FittingOutputs Vto, VP, γ’

Get nInputs

VP, γ’, φ, UT

Get Θ and β0Inputs

VP, IS, n, UT

Get new ISInputs

VG, γ’, φ, UT, Θ, β0, Weff, Leff, LETA, WETA

Get LETA and WETAInputs

VG, VP, Vto, γ’, Weff, Leff, VD

Get ID_EKV Calculate the transistor current ID, using the set of equations of the EKV model

Get ID_HspiceWrite .sp file Hspice simulation:

Id = f(VG,VS)

END

Error ID_EKV vs ID_HspiceOutputs

Write all the transistor EKV model parameters into a .xlsx file

Figure 3.1: Flowchart of the BSIM to EKV model extraction parameters


62

which means that the specific current can be obtained from the slope of √Ids(Vs). In Figure 3.2a a typical test circuit for simulating the transistor behaviour regarding Ids, is represented. The current Ids as a function of the source voltage, for different gate voltage values, is plotted in Figure 3.2b. It is clearly identifiable that a similar slope is obtained for all the curves repre-sented in Figure 3.2b, validating equation (3.11).

Vdd = 1.2V; Vg = 0.35-1.2V; Vs = 0.0-0.8V

a) Circuit for specific current extraction b) √Ids as function of Vs

Figure 3.2: EKV model - IS parameter extraction

The pinch-off voltage, VP, is determined by measuring the source voltage in saturation mode, when the transistor current, Ids, is in the order of half of specific current, Is [38]. Hence, in those conditions, the transistor is biased in moderate inversion region. The use of a simple circuit, as illustrated in Figure 3.3a, to simulate the transistor performance, does not guarantee a constant drain-source voltage when sweeping Vg. Therefore a small error arises from the channel length modulation, which affects mostly the short-channel devices. The circuit of Fig-ure 3.3b overcomes this limitation, where a constant Vds voltage is imposed by means of an Op-Amp, and its value is regulated by the resistor R, and the current source IR [38]. The pinch-off voltage characteristic obtained by simulation is represented in Figure 3.4.

a) Circuit for pinch-off voltage extraction,

simple circuit b) Circuit for pinch-off voltage extraction,

constant VDS

Figure 3.3: EKV model - pinch-off voltage (VP) parameter extraction

The first three EKV parameters, Vto, γ and φ, are determined from the previous results. The value of the threshold voltage, Vto, is the value of Vg when VP equals zero, which is eas-ily obtained by fitting the pinch-off voltage characteristic, represented in Figure 3.4, to an


63

equation of a straight line. Through a similar methodology, the values of γ’ and φ, are ex-tracted by fitting equations (3.7)-(3.8) to the same simulated pinch-off voltage characteristic.

Figure 3.4: EKV model - parameter extraction, VP as function of Vg

The next set of parameters, β0, Θ, UT, are determined by fitting equations (3.4)-(3.6) to the simulated characteristics of the specific current and pinch-off voltage, illustrated in Fig-ure 3.2b and Figure 3.4 respectively. In our approach, we have considered the thermal volt-age, UT, as a constant given by, UT=BT/q, where B is the Boltzman constant, T is the abso-lute temperature (K) and q is the electron charge.

Finally, to determine the parameters LETA and WETA, two different strategies were used. In one hand, the parameter LETA is obtained through the simulation of VP = f(Vg) for wide/short (Wmax, Lmin) transistors. On the other hand, the parameter WETA is obtained through the simulation of VP = f(Vg) for narrow/long transistors [37],[2]. In both situations, the simulated results together with the EKV model equation (3.9) are used for the curve fit-ting, making possible the extraction of the parameters LETA and WETA.

3.2.2 Parameters Extraction - Example

As a parameters extraction working example, the EKV model parameters obtained for UMC130 technology, and a NMOS transistor with length L=0.39µm and width W=50·L, are presented in Table 3.1. In Figure 3.5, the error between the transistor current, Ids, obtained with the EKV model and from simulations through BSIM model (HSPICE), is plotted. As it is possible to observe, the error range is perfectly acceptable.

Table 3.1: EKV model parameters (L=0.39µm and W=50L)

Vto (V) γ (√V) β0 (A/V2) Θ (-) UT (V/K) φ (V) Weff (µm) Leff (µm) LETA (-) WETA (-)

261.5e-3 175.0e-3 31.24e-3 1.394 25.9e-3 778.1e-3 19.4 0.37 6.85e-3 1.15e-6

To validate the EKV model parameters extraction for different transistor sizes, a com-parison between the current characteristic obtained either with the analytical model and with


64

simulations through HSPICE was made. To prove the validity of the EKV model to diverse transistor sizes, three sets of comparisons were done: i) constant length and variable width; ii) variable length and constant width and iii) varying both the transistor length and width.

Figure 3.5: Transistor Ids error between EKV model and simulation (HSPICE) results

For the first comparison scenario the transistor length was kept constant, L=0.39µm, and a maximum variation of ±80% in the transistor width, with respect to the value used for the parameters extraction procedure (W=50·L) was considered. In this analysis, four distinct comparisons were performed, respectively for W=(±80%)·50·L and W=(±40%)·50·L.

In Figure 3.6, the error between the analytical model and simulation results is illus-trated. As it can be observed, the error is still in the same range order of that obtained in Figure 3.5, with an average error less than 5%. The graphics shown in Figure 3.6, point out the robustness of the EKV model to variations in the transistor width.

a) L=0.39µm, W=10·L b) L=0.39µm, W=30·L


65

c) L=0.39µm, W=70·L d) L=0.39µm, W=90·L

Figure 3.6: Ids error between EKV model and simulation (HSPICE) results for L=const and W=variable

In the second set of comparisons the transistor width was kept constant, W=50·0.39µm, and a maximum variation of ±20% in the transistor length, with respect to the value used for the parameters extraction procedure (L=0.39µm) was assumed. As done for the previous analysis, also for this case, four distinct comparisons were performed, respec-tively for L=(±20%)·0.39µm and L=(±10%)·0.39µm.

In Figure 3.7, the error between the analytical model and simulation results is pre-sented. It is possible to observe throughout the results plotted in Figure 3.7 that the EKV model is moderately sensible to variations in the transistor length. This means, that to keep an average error around 5%, the transistor length variation is four times smaller compared to the case with variable width (constant length).

a) L=0.8·0.39µm, W=50 µm b) L=0.9·0.39µm, W=50 µm


66

c) L=1.1·0.39µm, W=50 µm d) L=1.2·0.39µm, W=50 µm

Figure 3.7: Ids error between EKV model and simulation (HSPICE) results for L= variable and W=const.

The last set of comparisons was made assuming four extreme cases, combining the maximum and minimum values of both the transistor length and width: L=(±20%)·0.39µm and W=(±80%)·50·L. In Figure 3.8, the error between the analytical model and simulation results is depicted. By inspection of the Figure 3.8, it is possible to state that the main error contribu-tor is the variation in the transistor length. It is easily observed that the values of the transistor length that leads to high errors in Figure 3.7, are the same in Figure 3.8. Although these val-ues occur for small values of the gate voltage, where the error may reach up to 20 or 30 %, the average error through all the gate voltage range remains around 5%.

a) L=0.8·0.39µm, W=10·0.39µm b) L=0.8·0.39µm, W=90·0.39µm


67

c) L=1.2·0.39µm, W=10·0.39µm d) L=1.2·0.39µm, W=90·0.39µm

Figure 3.8: Ids error between EKV model and simulation (HSPICE) results for L and W variable

3.3 Integrated Capacitors - Varactors

For implementing a tunable LC-VCO, using a variable LC tank, two approaches can be done; either using a variable inductance or a variable capacitor. The variable capacitor is usu-ally the chosen element, since its control is much easier than for an inductor. In general the variable capacitor is called varicap (variable capacitor) or varactor. In this document, varactor will be adopted.

The study of VCOs applications has attracted designers’ attention for the use of inte-grated capacitors, aiming at a fully on-chip circuit. Designing integrated capacitors is a well known technique, and can be implemented in any IC process. For the implementation of monolithic capacitors to be used in LC-VCOs, CMOS technology is used rather than BJT or BiCMOS technology. Generally, CMOS technology has the advantages of showing lower manufacturing costs, higher packing density, better performance with digital circuits, and less power dissipation when compared with BJT technology. Regarding BiCMOS technology, it has been shown that in the lower gigahertz frequencies, it exhibits poor quality factor – Q [39].

As stated before, nowadays the standard technology for implementing a capacitor, to be used in RF circuits, is CMOS technology. Varactors can be implemented either as a junction diode or as a MOS transistor. The junction diode operates in its reverse-biased region, repre-sented in Figure 3.9a, taking advantage of the parasitic capacitances between the diffusion layer and the substrate wells. Since they exhibit small tunable capacitance range, which goes down as the supply voltage scales down, junction diode varactors are adequate for applica-tions with limited tuning needs [40]. The quality factor of a junction diode varactor is usually quite good, reaching values higher than 50 @ 1 GHz.

If a reasonable large tuning range is needed, the MOS transistor should be used. Even so, some literature states that in practice, this range is no more than five times bigger than


68

that achieved with the junction diode [35]. Additionally, the quality factor remains fairly good across the full tuning range. For a varactor implemented with a CMOS transistor, the inversion and accumulation mode, illustrated in Figure 3.9b and c, are the most common configurations.

a) Junction diode b) Inversion MOS c) Accumulation MOS

Figure 3.9: CMOS Varactor

The simplest way to obtain a varactor from a CMOS transistor is by connecting together the drain, source and bulk (DSB). This transforms the transistor into a two terminal device, DSB and gate. The capacitance that appears between these two points varies with the applied voltage. However, this variation is not linear, as represented in Figure 3.10, and three regions of operation are defined: accumulation, depletion, and inversion. The inversion region can be split in other three sub-regions called: weak, moderate, and strong inversion.

Figure 3.10: Tuning characteristics for a PMOS capacitor (B=D=S)

As it is possible to infer from Figure 3.10, in the accumulation and the strong inversion region the capacitance, Cox, does not change with the applied voltage, VBG, and its value can be obtained by

ox

oxox T

SC ε=

(3.12)

where S and Tox are the transistor channel area and the oxide thickness, respectively.

The other three regions represented in Figure 3.10, present a variable capacitance for intermediate values of VGB. This capacitance variation occurs due to the small charge carriers’ mobility at the gate oxide interface, leading to a reduction of the capacitance when compared to Cox. The total capacitance, Cmos, can be modelled as a series of two capacitances, Cox and Cd, represented in Figure 3.11. The capacitance Cd is the equivalent of the parallel of Cb and Ci, which accounts for the modulation of the depletion region below the oxide layer, and the


69

variation of the number of holes at the gate oxide interface, respectively. If Cb is the dominant capacitance, the MOS varactor is working in the depletion region; if the dominant capacitance is Ci, the device is in moderate region; otherwise the MOS varactor is working in the weak inversion region.

Figure 3.11: PMOS varactor

The MOS varactor behaviour shown in Figure 3.10, is not adequated when working as the tunable device in a VCO. This means that, if the signal at the transistor gate is variable, as happens in a VCO, then the instantaneous capacitance, Cmos, changes with signal varia-tion. Even if the average value of Cmos during a full signal period is still function of the voltage VBG, the tuning performance of the VCO is usually poor due to the nonmonotonicity of Cmos.

To overcome the previous problem, the typical solution is to ensure that the transistor does not stay in the accumulation region for a wide range of values of VG, yielding a roughly monotonic function for transistor capacitance Cmos. This can be done by connecting the bulk terminal to the highest DC-voltage available in the circuit, as illustrated in Figure 3.9b. A comparison between the simulated Cmos-VGS characteristics of two equally sized PMOS varac-tors, is presented in Figure 3.12 [39]. The device never enters in the accumulation region, except for the capacitor with B=D=S, working only in the strong, moderate and weak region. This topology is called as an I-MOS capacitor. An equivalent behaviour can be achieved with an NMOS capacitor, but with the bulk connected to the ground. Although, the NMOS topology shows lower parasitic resistance, it is more sensitive to substrate noise, when compared with the PMOS varactor.

Figure 3.12: Tuning characteristics for an I-MOS varactor [39]


70

Like the I-MOS varactor, it is also possible to force the MOS varactor to work in the accumulation and depletion regions only. In the literature, this solution is referred to as being more attractive than I-MOS, since it can achieve a wider tuning range, with a lower parasitic resistance [39], and is usually called as A-MOS capacitor. To implement an A-MOS capaci-tor it is necessary to substitute the D-S diffusions p+, (see Figure 3.11) by bulk contacts. In Figure 3.13 a comparison between the simulated Cmos-VGS characteristics of two equally sized PMOS varactors, B=D=S and A-MOS, is presented. As illustrated in both figures, Figure 3.12 and Figure 3.13, either the I-MOS or A-MOS varactor have higher tuning range when com-pared with the B=D=S configuration. In this last varactor topology, the capacitance over the entire range of the VSG voltage just shows a valley during a small interval, which makes the average capacitance almost constant and without the possibility of changing it. On the other hand, the I-MOS or A-MOS varactor are characterized by a reasonable tuning range due to a control voltage that allows to shift the curve C(VSG) varying the average capacitance over the VSG voltage range. If a tunable capacitor is required the I-MOS or A-MOS varactor must be adopted.

Generally, when designing a tank, the five parameters that must be taken into consid-eration are: the quality factor (Q), the tuning range (TR), the self-resonant frequency, maxi-mum/minimum capacitance and the effective implementation area. The tuning range and the quality factor, can be calculate by

minmax

minmax

CCCCTR +

−±= or

min

max

CCTR =

(3.13)

and

RCfπ(res.)cicleperenergydissipated(cap.)cicleperenergystoredQ

21

≈=

(3.14)

Figure 3.13: Tuning characteristics for an A-MOS varactor [39]


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3.3.1 CMOS Varactor Model

In an LC-VCO, the tank circuit is of major importance since it is responsible for produc-ing the required oscillatory signal. Moreover, the varactor is the element which gives the oscil-lator the capability of being tuneable. In this section a mathematical model for the CMOS varactor characterization is presented. This model has two main advantages. Firstly, the ana-lytical model for the varactor capacitances is based on process and technological parameters, avoiding the undesired empirical/fitting factors. Secondly, the analytical transistor model, which is needed to determine the transistor current, is the well know EKV model, guaranteeing the accuracy of the results for low-voltage circuit design.

The EKV transistor model is suitable to perform the automatic CV-characterization of varactors, due to reduced number of parameters as well as the continuity of the model. Ac-cording to [41], the intrinsic capacitances of a varactor are obtained through the relative variation of the nodes charge against the node voltage, obtained by:

yxxy VQC ∂∂±= with BSDGyx ,,,, =

(3.15)

The capacitances in a MOS transistor are represented in Figure 3.14, where intrinsic as well as extrinsic capacitances are shown. In a varactor, the total capacitance is usually re-ferred to as the gate capacitance, since the drain, source and bulk are connected to a fixed voltage, which allows neglecting the drain/source – bulk capacitance. Additionally, overlap and fringing capacitances – extrinsic capacitances, Cextrinsic – must be accounted for. The varactor total capacitance can be obtained through

extrinsicBDSGSGDGBtotal CCCCCC ++++= )(

(3.16)

CGBiCGBovCGSi

CBSi

CGSov

CjS CBDiCjD

CGDi

CGDov

gDS

gm·VGS

GS

D

Figure 3.14: MOS transistor capacitances

In [41] and [42] simplified expressions to determine each of the intrinsic capacitances are proposed. The varactor intrinsic capacitances are obtained through the following set of equations:


72

( ) ( )[ ]22 5.0132

forrevforrevrevoxGS IIIIICC +++−=

(3.17)

( ) ( )[ ]22 5.0132

forrevrevforforoxGD IIIIICC +++−= (3.18)

( )[ ] [ ]oxGDoxGSqqoxGB CCCCnnCC −−⋅−= 11 (3.19)

( ) GSqSB CnC ⋅−= 1 (3.20)

( ) GDqDB CnC ⋅−= 1 (3.21)

where Irev and Ifor are the normalised reverse and forward current, respectively; nq is the slope factor, γ is the body effect parameter, and VP is the pinch-off voltage, obtained by

rrev iI += 25.0

(3.22)

ffor iI += 25.0 (3.23)

61021

−+++=

φ

γ

P

qV

n (3.24)

In nano-CMOS technologies, besides the intrinsic capacitances, the extrinsic (overlap and fringing) capacitances may be a major player in the varactor total capacitance. The tech-nology scaling down has brought two features to the transistors: narrow channel length (and a very small gate oxide thickness - nm) as well as a lightly doped drain, which makes the ex-trinsic capacitances linked to the drain and source regions a considerable part of the total C(V) characteristic. Moreover, in the extrinsic region the capacitance is bias dependent, and thus essentially influenced by the gate voltage [43]. The extrinsic capacitance may be deter-mined by:

( ) ( )( )ofgifgovextrinsic CVCVCC ++≈ 2 (3.25)

In equation (3.25) Cov(Vg) is the parallel plate capacitance associated with the electric field in the gate-to-drain/source overlap region; Cif(Vg) is the inner fringing capacitance asso-ciated with the inner electric field emerging from metallurgical junction source/drain to the un-derside of the poly-gate. Cof is the outer fringing capacitance, independent of the gate voltage, related to the electric field emerging from the sidewall of the poly-gate, ending at the source/drain region [43]. The gate overlap capacitance is here defined as in equation (3.26), where Lov is the effective diffusion length.

( ) ( )govoxgov VLCVC ⋅= (3.26)


73

Concerning the fringing capacitances, the model proposed in [44] is adopted. For the inner fringing capacitance the equation proposed for nano technologies, does not account for the bias dependence. Since this capacitance is strongly influenced by the gate voltage, a more accurate expression is presented in [43], where:

−−−=

2

max, 232

expf

ffbgifif

VVCC

φφ

(3.27)

The outer fringing capacitance is bias voltage independent, and may be calculated by:

+

⋅=

ox

polyoxof T

TC 1ln2

πε

(3.28)

Figure 3.15: Tuning characteristics for an I-MOS varactor

Figure 3.15 shows the characteristic of an inversion MOS varactor (I-MOS) – a transis-tor with B=D=S, working only in the strong, moderate and weak region – obtained with the proposed varactor analytical model, for different tuning voltages, namely 0.2V (I), 0.4V (II) and 0.6V (III), against simulations obtain with HSPICE (+) software. The relative error for the mean capacitance was less than 4% in all cases. For those examples, the UMC130 CMOS technology, a transistor width of 10 µm and length of 0.8 µm, with a supply voltage of 1.2 V, was considered. The results in Figure 3.15 show the accuracy of the varactor model thus guaranteeing its adequacy to be integrated in an optimization based design tool.

3.4 Applicability of the Model to RF Frequencies

Any electrical circuit may be characterized by a number of equivalent circuit parameters, such as their transfer matrix, impedance matrix, admittance matrix, and scattering (S-


74

parameters) matrix. Among this list, S-parameters are the most used in microwave design, since they are easier to measure and to work with at high frequencies than other kinds of two-port parameters. S-parameters analysis are said to be conceptually simple, analytically convenient and capable of providing detailed insight into a measurement and modeling prob-lem [45]. However, S-parameters are linear by default, which means that, they represent the linear behaviour of a two-port network. In other words, S-parameters are small signal parame-ters by definition. For a transistor as an example, the S-parameters do not reflect non-linear amplification phenomena.

Yet, two-port parameters of non-linear components like transistors or diodes vary as a function of input power. Therefore, in RF simulators, all S-parameters of nonlinear electrical elements are represented by a 2x2 S-parameter matrix versus input power at port-1 for for-ward and port-2 for reverse operation. This data set has been accepted as a convenient means of characterizing nonlinear devices by their large-signal S-parameters and has been successfully used for designing power amplifiers, oscillators, etc [46].

Despite the undoubted qualities that S-parameters shows when applied to circuit analy-sis, they are not used in this work. The challenge to push design rules to the limit, gathered with the increase speed of digital circuits and consequently analog systems into the gigahertz region, requires the use of concurrent time and frequency domain measurements and/or analysis. To fulfil this new requirement, in this work the analytical models adopted are based in technological files, as these files are created taking into account both frequency and time domains, as illustrated in Figure 3.16.

Device Under Test

Frequency Domain Measurements Time Domain Measurements

Physical Layer Test System (software)

Simulator Engines(HSPICE, Smartspice, ADS, CST, …)

S-Pa

rameter

s

Time

Dom

ain

S-Parameters

Model Extraction Tool

Topo

logica

l Mod

els

Beha

viou

ral

Mod

els

Figure 3.16: Overview of the several ways to develop electrical models for circuit simulators [47]


75

In this work, the EKV MOS Transistor model parameters are obtained through a proce-dure that is based on simulations of the device by using HSPICE simulator. As it is possible to see in Figure 3.16, the technology files that are used by circuit simulators, such as HSPICE, are generated taking into account real measurements in both frequency and time domains. Afterwards, S-parameters as well as topological and behavioural models are used to create a final technology file that can be used by a circuit simulator engine. So, it is our un-derstand that the EKV MOS Transistor model used in this work also reflects the behaviour in frequency and time domains, thus being suitable for applications in the range of RF frequen-cies.

3.5 Conclusions

This chapter has discussed the use of transistor EKV MOS Transistor Model and its application either for the characterization of the transistor current behaviour, or for the estima-tion of the transistor capacitances when used as a capacitor. Also, the extraction process of the EKV model parameters was presented, showing the non dependency on fitting parameters. Due to its simplicity, regarding the number of equations, and the characterization of the tran-sistor behaviour from weak to strong inversion regions through a single equation, the EKV model is fairly suitable to be included in an optimization process.

The next chapter will address the analytical models of integrated inductors. The focus will be pointed to the two well known inductor equivalent circuits, the simple and double π-model, and their performances over frequency will be discussed.

77

4 Spiral Inductor

This chapter is motivated by the need to optimize the design of an integrated inductor, aiming its inclusion in a high level optimization procedure. For that purpose, accurate and technological dependent models are needed. In this study, the most appropriate inductor model is identified, and its performance is compared with those obtained with an electromag-netic simulator.

4.1 Introduction

Until the last century, the most convenient manufacturing processes for implementing high performance transceivers were those using off-chip passive elements due to their high quality factor (Q) [48]. However, modern CMOS processes have reached a maturity that makes them suitable for implementing fully integrated radio-frequency devices fulfilling the re-quirements of the wireless standards working at the GHz frequency range. Due to their low cost and ease of process integration, on-chip spiral inductors are widely used in analog blocks of RF integrated circuits, such as voltage-controlled oscillators, low-noise amplifiers and pas-sive-element filters [49]. The very first standards available for on chip inductors are in the range of a few nH with a quality factor (Q) below ten, depending on the technology and for an operating frequency below 6 GHz. Nonetheless, as the process technology improves and the number of metal layers increases, the quality factor (Q) of the passive elements is im-proving [50].

Fabrication of inductors on the same substrate as the remain of an RF circuit can elimi-nate the need of external connections, dropping down issues such as electrical and magnetic coupling and path and bond wire parasitic. Moreover, this has lead to new circuit techniques that can attenuate some of the constraints regarding the trade-offs in the RF design, e.g. noise, as most of the elements are built on-chip. Regarding an integrated LC tank, the induc-tor is its most vital component, since the inductor low quality factor (Q) affects phase noise

Spiral Inductor

78

performance and determines the power dissipation [50]. In parallel with the quality factor (Q), the other two most important parameters of monolithic inductors are the self-resonance fre-quency, and the area, all of which strongly depend on the layout and the properties of the IC technology. As is shown in Figure 4.1, the LC tank occupies approximately 50% of the VCO area.

Figure 4.1: The photomicrograph of an LC-VCO [51]

Notwithstanding the widespread use of integrated inductors, their design is still a quite challenging task due to the complexity of design options that must be adopted aiming at minimizing the inductors high frequency poor performance and their subsequent impact on the circuit efficacy. This poor performance is due to the large effect the technology parasitics have on the usually required small value of inductance. As a result, significant effort has been em-ployed in investigating silicon planar inductors, their associated models and methods of im-proving their performance. Modern fabrication costs are putting pressure on designers to pro-duce ready to market designs in less iteration. This reduces the opportunity for using a spe-cific process fine-tune S-parameter based methodology [52] or to using empirical [53] mod-els. On the other hand accurate SPICE level inductor models are restricted to an insufficient number of geometries forcing designers of custom inductors to a time consuming process of electromagnetic (EM) simulation. Furthermore, the use of either of the previously mentioned approaches, although producing accurate results, does not give the designer a qualitative in-sight into which parameters should be altered in order to improve the inductor behaviour. Thus, scalable and physically-based models are of vital importance for the designer to make decisions regarding the improvement of inductor behaviour. Furthermore, such models also allow the optimization of the inductor within the circuit design process.

The last two decades were very fruitful regarding new proposals for the inductor analyti-cal modelization. On the basis of a wide diversity of models, is the single (or simple) π model, introduced by [54]. The single π model is usually described by an electrical circuit equivalent, where electrical resistance (R), inductance (L) and capacitance (C) at each differ-ent level is illustrated in Figure 4.2a. Although more accurate models have been developed, nevertheless more complex, the inductor π model is simple and gives accurate results for fre-

Spiral Inductor

79

quencies of operation below 1 GHz. Designers who understand this simple model, easily will be familiarized to more complex models. The model here described is valid for a single metal layer, with the topology shown in Figure 4.2b.

a) b)

Figure 4.2: Integrated spiral inductor: a) Planar inductor simple-π model, b) Single metal layer topology

Endeavouring to improve the single π model performance for higher frequencies than 1 GHz, the influence of skin effect for the estimation of the metal resistance was introduced in [55] and [56]. Going a step forward, a lightly modified circuit model in proposed in [57], and illustrated in Figure 4.3a. The resistance RC is introduced to reflect the substrate coupling effect on the circuit behaviour. Although, to keep the circuit model frequency independent, two-port measurements are used to model the inductor physical behaviour over a wide fre-quency range. A different approach, yet based in the π model, where the inductor perform-ance is evaluated from the energy point of view, taking into account the frequency depend-ency of the lumped elements, is presented in [58]. Characterization based on the S-parameters measurement is performed, and then a single π type lumped-element equivalent circuit model is obtained by fitting experimental data. An enhancement to the single π model, where a substrate-coupled model that accounts for eddy currents that appear at substrate level is also proposed in [59], represented by Lsub and Rsub in Figure 4.3b. The authors stated that the proposed model, expressed by monomial equations in terms of the inductor geometry, clarifies and describes why a reduction of the equivalent resistance occurs with in-creasing frequency as well as the inductance and quality factor. The main reason for these phenomena is the high conductivity of the silicon, allied to the capacitive coupling between inductor tracks and the substrate, are perfect condition for a current to flow.

A complete different approach, aiming to reduce the parasitic effects in the inductor be-haviour, and consequently reducing the complexity of the analytical equations needed to char-acterize the inductor, a new mechanism at the fabrication level to improve both the quality factor and better frequency response of on-chip inductors, by means of proton bombardment to the substrate, which increases its resistivity, is proposed in [60].

Spiral Inductor

80

a) b)

Figure 4.3: Integrated spiral inductor: a) modified model [57], b) substrate coupled model [59]

A wide-band physical and scalable double-π model equivalent circuit for on-chip spiral inductors is proposed in [61], and will be analysed in a forward subsection. Although the double-π model accounts for the frequency dependence of resistance and inductance, there is a singular point above the resonance frequency, where the prediction of the impedance is too low, impairing the accuracy of the model.

A qualitative representation of the trade-off between complexity and accuracy of four of the previously mentioned inductor models is depicted in Figure 4.4.

Figure 4.4: Comparison between complexity vs accuracy of different inductor models

The main challenge regarding inductor design is to accurately model its losses. The loss in a monolithic inductor stems from three major sources: metal wire resistance, capacitive and magnetic coupling to the substrate. Determined by the substrate resistivity and the size of the inductor, the last two effects limit the quality factor (Q) at high frequencies. So, prediction of an inductor quality factor (Q) could be much more difficult than calculating their inductance. The planar geometrical structures are realized in integrated circuit metallization processes, ei-ther in bipolar or CMOS technology. Modern IC metallization processes offer four to nine metal layers which are intended for digital circuits wiring, so this technology can be used to build integrated inductors [3]. However, for the simplicity of analyses, the models described in this chapter will just consider one metal layer.

Spiral Inductor

81

The inductor models are based on geometric design parameters, which are represented in Table 4.1, and illustrated in Figure 4.5, for the particular case of a square inductor. The closed-form expressions that compose the inductor model, should provide design accuracy within about 10% [62], nevertheless, the fundamental aspect is to offer the designer a straightforward starting point for a final inductor design.

Table 4.1: Integrated inductor layout parameters

Symbol Variable Symbol Variable

w track width din Inner diameter

t track thickness dout Outer diameter

l track length n Number of turns

s track to track distance Ni Integer number of n

Figure 4.5: Layout parameters of a square inductor

4.2 Lumped Elements Analytical Characterization

Integrated inductors are usually described by a circuit equivalent, and for that propose the inductor single π model, early presented, has been widely used. The model represents not only the spiral inductance and resistance, but also the parasitic elements. So, in the π model, Ls and Rs represent the inductance and resistance of the spiral, respectively. The narrow proximity between the inductor tracks and underpass, form a capacitive coupling represented by Cs. The oxide capacitance between the spiral and the substrate is modelled by Cox. The resistance and capacitance of substrate, referred to ground, are modelled by Rsi and Csi, re-spectively. Each of the previous parameters, are strongly dependent of the inductor shape, as well as the technological process.

4.2.1 Inductance (Ls) Models

As aforesaid, the evaluation of Ls requires deep knowledge of the technology, shape and the influence of the parasitic elements. Due to the complexity of this calculation, several approaches have been proposed for the evaluation of Ls. From the several inductance models

Spiral Inductor

82

in literature, some are based on fitting process from values obtained experimentally, others are based on empirical equations. In the next subsection, a brief description of those models is done.

4.2.1.1 Greenhouse Approximation of Grover Formulae

The Greenhouse Approximation [63] is the starting point for most works published in the field. For the self inductance of an inductor with a square cross section, Greenhouse pro-posed

+++

+=

ltw

twllLS 3

50049.02ln002.0 (4.1)

where the inductance is given in µH, if all dimensions were in cm.

4.2.1.2 Modified Wheeler Formula

This model is a simplified approach of Wheeler’s original formulas [64], which were proposed for spiral inductors. This approach leads us to

ρµ

2

2

01 1 Kdn

KL avgS +

= (4.2)

where

inout

inoutdddd

+−

=ρ , 2

inoutavg

ddd += and ( )snnwdd inout 122 −++=

K1 and K2 are coefficients that allow the model to be adapted for several inductor shapes, and are seen in Table 4.2. This will be the model adopted in this work.

Table 4.2: Modified Wheeler Formula coefficients

Ind. shape K1 K2

Square 2.34 2.75

Hexagonal 2.33 3.82

Octagonal 2.25 3.55

4.2.1.3 Data Fitted Monomial Expression

Based on data fitting from measured data, equation (4.3) was obtained [65]. The co-efficients β and αi are layout dependent, represented in Table 4.3. The inductance is given in µH.

54321 αααααβ sndwdL avgoutS = (4.3)

Spiral Inductor

83

Table 4.3: Data Fitted Monomial Expression coefficients

Ind. shape β α1 α2 α3 α4 α5

Square 1.63e-3 -1.21 -0.147 2.40 1.78 -0.030

Hexagonal 1.28e-3 -1.21 -0.174 2.47 1.77 -0.049

Octagonal 1.33e-3 -1.21 -0.163 2.43 1.75 -0.049

4.2.1.4 Current Sheet Approximation

The idea under this model is to approximate any inductor layout to the square shape. With this approach [65], the effect of neglecting the mutual inductance is minimized, because between orthogonal current sheets the mutual inductance is zero. The formula to evaluate the inductance of a spiral inductor is

++

= 2

4321

2

ln2

ρρρ

µccccdn

L avgS (4.4)

where ci are layout dependent coefficients, represented in Table 4.4.

Table 4.4: Current Sheet Approximation coefficients

Ind. shape c1 c2 c3 c4

Square 1.27 2.07 0.18 0.13

Hexagonal 1.09 2.23 0 0.17

Octagonal 1.07 2.29 0 0.19

Circle 1.00 2.46 0 0.20

The results obtained through this methodology for non-square shapes, have shown sig-nificant deviation when compared to those achieved with electromagnetic simulators.

4.2.1.5 Jenei Approximation of Grover Formulae

Based on several formulas proposed by Grover, this approximation was derived for symmetrical inductor shapes [66]. The inductance is evaluated taking into account that the inductor presents a regular growth of segments, which leads to a linear relationship between the total length and the inner diameter.

( )

−

+

= 2.0ln2

0twn

lLS πµ

(4.5)

where

( ) ( )swNNdnl iiin ++++= )14(14 (4.6)

Spiral Inductor

84

4.2.2 Inductor Resistance, Rs

The electric resistance in a metal conductor is given by the well known equation (4.7), reflecting the resistance dependence on metal conductivity, σ, as well as metal dimensions reflected by w, l and t.

twlRs σ

= (4.7)

The previous equation is valid for a conductor where the current density is uniform, typically for DC and low frequencies circuits. On the other hand, as frequency increases, and due to the magnetically induced eddy currents on the conductor, a non-uniform current distribution appears. This effect is known as the skin effect, as for high frequencies, the useful conducting area in a conductor is reduced. The skin depth can be determined by [67].

fπµσδ 1

= (4.8)

Due to skin effect, for high frequencies equation (4.7) is converted into

( )δδσ ts ewlR −−

=1

(4.9)

For a planar conductor the previous equation just takes into account the top and bottom walls of the conductor. This approximation is not a problem if the conductor width is greater than its thickness. If not, neglecting the conductor side walls, can introduce a huge error is resistance estimation [68]. To overcome this gap [69] proposed the following equations to evaluate the conductor resistance

twlRR dcacf σ

==→0lim (4.10)

( )twwlkRkR hfacf +

==∞→ δσ2lim

(4.11)

( )22hfdcacs RkRRR +==

(4.12)

where k is a correction factor and takes the value 1.2, considering the edge behaviour of the metal.

4.2.3 Crossover Capacitance, Cs

This capacitance appears between the spiral and the underpass necessary to connect the inner turn to the outside of the spiral inductor. For the evaluation of this capacitance, all overlap capacitances are considered [68], [70],

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85

21

2

MoxM

oxcs twnC

−=

ε (4.13)

where εox is the oxide permittivity, nc is the number of overlaps and 21 MoxMt − is the oxide

thickness between the spiral upper and lower metal.

4.2.4 Oxide Capacitance, Cox

The capacitance, Cox, models the capacitive effect arising from the spiral metal and the silicon substrate. A usually adopted equation to estimate this capacitance is [68], [70]

lwt

Cox

oxox

ε5.0= (4.14)

where tox is the thickness of the SiO2 between the inductor and the substrate and lw defines the area of the spiral.

4.2.5 Substrate Resistance (Rsi) and Capacitance (Csi)

The substrate parasitic elements are a consequence of the time-varying magnetic field that penetrates into the silicon substrate, leading to power loss as well as to a reduction in spiral inductance. The substrate resistance is given by [68], [70]

lwGR

sisi

2= with

si

sisi h

G σ= (4.15)

where Gsi is the substrate conductance per unit area, σsi and hsi are the substrate height and conductivity, respectively.

The substrate capacitance is given by [68], [70]

lwCC subsi 5.0= with si

rsub h

C εε0= (4.16)

4.2.6 Inductor Quality Factor (Q)

The inductor quality factor is usually adopted as the characteristic to be used when comparing the inductors performance, which is limited by the losses through undesired cur-rents in the substrate and in the series resistance of the inductor windings. The energy deliv-ered to an inductor is stored in the magnetic field but, there will be some energy stored in the electric field, associated to the unwanted parasitic capacitance. These three factors, magnetic and electric energy, as well as the circuit resistance, have an important role in the inductor performance. Among several definitions of the quality factor (Q) that can be found in litera-ture, in this work the definition presented in [71] is adopted, where

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86

cyclenoscillatiooneinDissipatedPowerAverageEnergyElectricPeakEnergyMagneticPeakfQ −

= 02π (4.17)

From eq. (4.17) it is possible to realise that the quality factor (Q) is equal to zero, when the peak magnetic energy is the same as the electric energy; this phenomenon is called self-resonance. This also means that an inductor maintains is behaviour for operating frequen-cies below the self-resonance frequency, but for higher frequencies the component exhibits capacitive performance; moreover, a negative quality factor (Q) is achieved. Figure 4.6 illus-trate the inductor behaviour against frequency.

Figure 4.6: Inductor behaviour vs frequency

For an accurate prediction of Q, the parasitic effects cannot be neglect. The π model presented in Figure 4.2a takes into account a set of various parasitic and loss elements, al-lowing to rewrite eq. (4.17) as function of the passive components. The Q is usually calcu-lated reducing the two ports of the π model, to a single port by grounding the second port. This configuration aims to simplify the analysis of the Q behaviour. Figure 4.7a shows the π model with the second port grounded, and its one port equivalent circuit. When the second port is connected to ground, the circuit may be transformed into the circuit in Figure 4.7b.

a) b)

Figure 4.7: One port π model circuit: a) One port π model, b) One port equivalent circuit

The parasitic elements Cox, Rsi and Csi are replaced respectively by its parallel equivalents Cp and Rp, which continue to be frequency dependent elements, given by

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87

( )2

2

221

ox

sioxsi

sioxp C

CCRRC

R ++=

ω (4.18)

( )( ) 222

22

11

sisiox

sisisioxoxp

RCCRCCCCC

++

++=

ωω

(4.19)

Finally, it is now possible to calculate the energy associated to each of the passive elements in the equivalent circuit, in order to obtain the quality factor (Q). The magnetic energy is re-lated with the inductance Ls and given by

( )[ ]ss

ssmagneticpeak RL

LUILE+

== 2

202

max 221

ω (4.20)

where U0 is the peak voltage at the inductor branch. On the other hand, the electric energy store in parasitic capacitances is

( )22

1 202

maxps

electricpeakCCU

CUE+

== (4.21)

at last, the energy dissipated in one cycle, related to both resistances, is given by

( )( )

++=+=

22

20 1

22

ss

s

psRpRloss

RLR

RUTPPE

ωωπ (4.22)

Replacing equations (4.20)–(4.22) into (4.17) come

( ) ( )

+−+−

+

+

= psspss

s

s

ssp

p

s

s CCLCCLR

RLRR

RRLQ 2

2

21

1

ωω

ω (4.23)

The previous equation still may be separated in three terms, which characterizes the in-ductor performance. The first one represents an ideal inductor, where just the magnetic energy stored and the ohmic losses are considered. The middle term, concerns to the substrate losses. The last term is related with the self-resonance factor; as high the frequency is, lower will be the Q. The self-resonance frequency can be obtained making the third term equal to zero.

A more expedite process to calculate Q, could be achieved by measuring the input im-pedance of the circuit with one port grounded. The energy stored in the inductor, is linked to the imaginary part of the input impedance Zin; whereas the real part of Zin is proportional to the energy dissipated in resistances. With this approach, eq. (4.23) is reduced to

( )( )ine

inmZZQ

ℜℑ

= (4.24)

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88

4.2.7 Model Validation

Since the very first years of the 90s, when the integration of a spiral inductor using a silicon fabrication technology was a reality, analytical models to predict the behaviour of such passive elements has increased. This was a major step for designers that could characterize the inductor independently of their fabrication technology. Yet, some incoherencies estimating its losses, mainly due to the large number of parasitic effects, were a core issue.

In the end of the 90s, a free software called ASITIC that characterizes the behaviour an inductor based in its geometry and technology parameters was developed. The main ad-vantage of ASITIC relies on both results accuracy and low computational time.

The results here presented, has as goal to show the validity of the π model at low fre-quencies, it means, below 1 GHz. The analytical results are compared against those obtained with ASITIC. The performance of a square planar inductor, implemented in a single metal layer, for operating frequency from 0.1 up to 2.0 GHz in UMC130 technology is addressed. The inductor geometric characteristics are those in Table 4.5 and illustrated in Figure 4.8.

Table 4.5: Square planar inductor dimensions

Track Width - W (µm) 15.0

Inner Diameter - Din (µm) 75.0

Outer Diameter - Dout (µm) 300.0

Number of Turns 6.5

Space between Tracks (µm) 2.5

Figure 4.8: Square planar inductor

In Figure 4.9a – Figure 4.12a results obtained with the simple π model and ASITIC, re-garding the inductor characteristics such as inductance, impedance (real and imaginary parts) and the quality factor, are plotted. The results obtained with the simple π model are presented by a continuous line (blue line) and those obtained with ASITIC are pointed out by the plus

Spiral Inductor

89

sign (green marks). On the right side, Figure 4.9b – Figure 4.12b, the error obtained between both methods is offered.

a) Inductance variation with frequency b) Inductance error

Figure 4.9: Spiral inductor inductance, π model vs ASITIC

a) Resistance variation with frequency b) Resistance error

Figure 4.10: Spiral inductor resistance, π model vs ASITIC

a) Reactance variation with frequency b) Reactance error

Figure 4.11: Spiral inductor reactance, π model vs ASITIC

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90

a) Quality factor variation with frequency b) Quality factor error

Figure 4.12: Spiral inductor quality factor, π model vs ASITIC

As mentioned before, the simple π model is quite good to characterize the inductor per-formance for frequencies up to 1.0 GHz, where parasitics phenomena have insignificant ex-pression. The graphics in Figure 4.9b – Figure 4.12b shows an average error lower than 5%, if considered an operation frequency range from 0.1 to 1.0 GHz. Above the brake-point fre-quency of 1.0 GHz, the error starts growing with an exponential behaviour, and at 2.0 GHz the error is around 25% for the inductance, resistance and quality factor. The results pre-sented in this section highlight the need of more accurate inductor model, if its characteriza-tion for frequencies higher than 1.0 GHz is aimed.

4.3 Inductor Double-π model

The double-π model aims to overcome the main drawback of the inductor π model which is its lack of accuracy for frequencies above 1 GHz. This occurs because the simple π model´s equation don’t take into account some effects, such as more complex issues regard-ing skin and proximity effects, ohmic losses in the conductive substrate, losses due to eddy current in the underlying substrate (due to the penetration of the magnetic field into the con-ductive silicon) and energy losses caused by the nonzero resistivity in metal lines, which have strong impact in the inductor behaviour for high frequencies. Nevertheless, it is possible to model these effects using additional elements to the π model. The double-π model, based on the well known π model, was proposed by [61] with the aim of modelling the frequency de-pendence of resistance, R(f), and inductance, L(f), as a result of the skin and proximity ef-fects, and is represented in Figure 4.13.

The set of equations used to characterise the behaviour of the inductor, through the double-π model, can be divided in 3 blocks; DC inductor parameters, Substrate Network and Ladder Circuit elements, respectively. The following subsections are dedicated to present how to estimate the value of the elements of each mentioned block.

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91

Figure 4.13: Inductor double-π model equivalent circuit

4.3.1 DC inductor parameters

The accuracy of the equations presented in 3 and 4.2.2 to estimate the inductor induc-tance (Ls=Ldc) and resistance (Rs=Rac) at low frequency have been verified for a wide range of inductor configurations, and they still are used in more complex models, such as the dou-ble-π model.

4.3.1.1 Metal-to-metal capacitance, Cc

The metal-to-metal capacitance Cc occurs due to the proximity of inductor tracks, see Figure 4.14, where is also represented the metal-to-substrate capacitance, Cox. Both capaci-tances are modelled as the summation of three rational functions which simulate three flux components, and are obtained by (4.25) and (4.27) [72].

179.11612.0

144.10944.0

9801.0874.1158.1

592.17428.0

059.2144.1

+

+

+

+

+

+

=

stt

sww

sww

stt

stC

ox

ox

ox

oxmetal

ox

cε

(4.25)

Figure 4.14: Cross section of a planar inductor

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92

The metal-to-metal capacitance Cc then must be scaled with their effective coupling lengths. Considering that exists coupling capacitances among all the inductor inner tracks, then the total capacitance Cc is

lCC ctotalc =_ (4.26)

However this assumption is not totally true as the outer and inner turns do not have a neighbour track in one side. So, the length considered in (4.26) must take into account this issue.

In [72] is also proposed a new approach to estimate the metal-to-substrate capaci-tance, Cox.

1204.0

193.3193.3

532.4

510.1171.1

702.0217.2

+

⋅

+

+

+

+=

oxmetal

metal

oxoxoxox

ox

ttt

tss

tss

twC

ε (4.27)

Also here, Cox must be scaled by the spiral total length,

lCC oxtotalox =_ (4.28)

4.3.2 Substrate Network

Concerning the substrate elements, there’s the need to model the ohmic losses in the conductive silicon substrate, which are encapsulated in Rsub and Csub. A third element is Rsc which represents the electric coupling between lines through the conductive substrate, and given by

substrate

substratesc tl

PNR ρ5.1= (4.29)

where N is the number of turns and P is the metal line pitch (metal width plus the metal spacing from edge to edge).

As a way of predicting the frequency influence in substrate losses, Rsub and Csub should be frequency dependent equations. The following equations are obtained from [73], as sug-gested in [61], the proposer of the double-π model. Considering Figure 4.15, substrate losses are represented in b) by C2 and GS elements, and given by equations (4.30) and (4.31), respectively.

( )( )whF

hC oxideeff

,,

1

202

εεε= (4.30)

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93

a) Metal-oxide-silicon interconnect structure [73]

b) Configuration-based inter-connect circuit model

c) Telegrapher’s equation model representation of single

conductor interconnect

Figure 4.15: The basic metal-oxide-silicon structure and its equivalent circuit.

( )[ ]( )whF

whG substrates ,2

10111

2

5.02

−++=

σ

(4.31)

where

( )( ) 5.01012

12

1,wh

heff+

−+

+=

εεεε (4.32)

( )

≤

−+−+

>

+

= 1

144.042.2

1

14

8log5.0

,6 wh

wh

wh

hw

whh

wwh

whF

(4.33)

The above equations considered element values defined per area, which means that the real values of Rsub and Csub must be scaled by the total spiral length

lG

RS

sub1

= and lCCsub 2= (4.34)

4.3.3 Ladder Circuit Elements

The set of equations necessary for the computation of the extra elements behaviour are represented in eq. (4.35) to (4.43) [61], [72].

swP += (4.35)

23.1240 Nm= (4.36)

( ) dcrs RnR 11 −+= (4.37)

dcr

s Ln

kL

−= 5.157.31 (4.38)

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94

srp RnR = (4.39)

r

sp n

LL315.0

= (4.40)

psm LLkL = (4.41)

rdccrit

dc nL

Rm

k

=

ω315.0

(4.42)

sheetcrit RwP

20

1.3µ

ω = (4.43)

4.3.4 Quality Factor Evaluation

In spite of the complexity of the model, an equivalent circuit model considerably reduces computation time and supports optimization design. Moreover, as a result of the complexity of the system of equations involved, it is not possible to predict the inductor inductance and quality factor with a single symbolic equation. Furthermore, a fully symbolic characterization is also not easily generated and a semi-symbolic approach is considered. Thus, circuit analysis is needed, such as Kirchhoff’s Laws and electromagnetic induction theory, for obtaining the value of the input impedance of the one port equivalent circuit, and then the inductance and the quality factor (Q) can be calculated. The following set of equations, will be used for the circuit analysis.

20 sLjZ ω= (4.44)

221 pp RLjZ += ω (4.45)

22 sRZ =

(4.46)

2mM LjZ ω=

(4.47)

ssC CjZ ω1=

(4.48)

ccC CjZ ω2=

(4.49)

oxC CjZ ox ω2=

(4.50)

oxmidoxC CjZ ω1_ =

(4.51)

scscR RZ =

(4.52)

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95

( ) ( )2//2_ subsubmidsub RCjZ ω=

(4.53)

( ) subsubsub RCjZ //1 ω=

(4.54)

As aforementioned, applying Kirchhoff’s Laws, it is possible to obtain a cluster of equa-tions in order to estimate the input impedance Zin, in order to estimate the inductor inductance and the quality factor (Q) according to eq. (4.24). Those equations are presented in a matrix 7-by-7, see Appendix I.

4.3.5 Model Validation

The validity of the double-π model was made by comparison of the analytical results and those obtained with ASITIC software. The performance of two square planar inductors, implemented in a single metal layer in UMC130 technology, designed to have an inductance of 4 nH at 2 and 6 GHz, is addressed. The two inductors geometric characteristics are pre-sented in Table 4.6.

Table 4.6: Square planar inductor dimensions (4 nH @ 2-6 GHz)

4 nH inductor 2 GHz 6 GHz

Track Width - W (µm) 9.75 6.75

Inner Diameter - Din (µm) 140.25 121.25

Outer Diameter - Dout (µm) 221.00 181.00

Number of Turns 3.5 3.5

Space between Tracks (µm) 2.5 2.5

The behaviour of both inductors, related to inductance and quality factor performance, for frequencies up to the resonance frequency is offered in Figure 4.16 - Figure 4.19. The results obtained with the double-π model are illustrated by a continuous line (blue line) and those obtained with ASITIC are given by the plus sign (green marks). On the right side (b) figures), the error obtained between both methods is offered.

Regarding the inductance behaviour, both inductors show a very good agreement with ASITIC results, in the vicinity of the desired operating frequency. Although, as the frequency rises, it is notorious that the double-π model achieves the resonance (when the inductance becomes zero) prematurely when compared with ASITIC. However, the resonance frequency is not a desired operating point, and the inductor should be working at a point far behind the resonance, where the inductance curve shows a linear behaviour. The error for the inductance performance is quite small in the neighbourhood of the desired operating frequency, on the other hand, when the frequency goes in the direction of the resonance point, the error in-creases.

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96

Concerning the quality factor characteristic, both curves obtained with the double-π model and ASITIC show an identical behaviour. As well as for the inductance, the quality fac-tor curve obtained with the analytical model reaches the resonance point earlier than the curve obtained with ASITIC. Moreover, the maximum quality factor achieved is slightly higher in the double-π model characteristic than in ASITIC. As the quality factor curves have a high gradi-ent, the average error is higher when compared with the inductance, however quite accept-able. The validity of the double-π model for the characterization of the planar inductor per-formance was demonstrated with the results presented in this section.


Figure 4.16: 2 GHz Spiral inductor inductance, double-π model vs ASITIC


Figure 4.17: 2 GHz Spiral inductor quality factor, double-π model vs ASITIC


Figure 4.18: 6 GHz Spiral inductor inductance, double-π model vs ASITIC

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97


Figure 4.19: 6 GHz Spiral inductor quality factor, double-π model vs ASITIC

4.4 Conclusions

In this chapter an integrated inductor analytical model was identified, that characterizes with good accuracy the inductor behaviour, concerning its inductance and quality factor. Re-garding the double π-model, and for the simplicity of analytical analyses, the use of Kirchhoff’s Laws and electromagnetic induction theory, allows to obtain the value of the input impedance of the one port circuit, and then the inductance (L) and the quality factor (Q) can be calculated. When compared with electromagnetic simulator results, the inductor L and Q, obtained through the analytical model, shows and average error below 10%.

In the next chapter the design optimization of a LC-tank circuit will be address. The CMOS transistor and inductor analytical models will be incorporated in a optimization process, that uses evolutionary algorithms, and the best design of a LC-tank circuit, for certain input specifications, aims to be achieved.

99

5 VCO Tank Optimization

This Chapter presents the optimization-based design of radio-frequency integrated spiral inductors and capacitors, as they are crucial elements for the LC voltage controlled oscillator’s performance. The chapter starts with an overview regarding the LC tank characteristics, where the highlights are put on the inductor and varactor design. Afterwards the focus goes to the optimization procedure, which is based in evolutionary algorithms, as the path for optimal de-sign. The results obtained will be compared with those obtained through well-known simula-tor(s).

5.1 Introduction

As LC-VCOs are based on LC-tanks, the properties of the tank must be considered for the oscillator performance, since it determines the frequency of oscillation. Moreover, LC-tank based oscillators are one of the most popular configurations in RF transceivers due to their fairly good performance [74]. As a first approximation for LC tanks, the tank circuits in Figure 5.1 is considered. When energy is injected into the circuit, the LC circuit is capable of trans-ferring that energy between the inductor and capacitor. As is well known from circuit analysis theory, reactive elements store energy for one half a cycle, returning that same energy to the circuit in the next half a cycle. As inductors and capacitors perform this energy transfer in op-posite cycles, when one of the elements is receiving energy, the other one is releasing, with a certain frequency. It is possible to say that this task is done with a determined oscillation fre-quency.

If we considered the ideal LC tank, represented in Figure 5.1a, once the energy is in-jected into the circuit, it would remain there forever, since there are no losses in ideal reactive elements. However, either in real integrated or discrete circuits, resonators suffer from ohmic losses, represented by Rs and Rc in Figure 5.1b, leading to the need of a feedback circuit to

VCO Tank Optimization

100

restore energy and to keep a continued oscillation. Usually the circuit in Figure 5.1b is con-verted to its parallel equivalent, represented in Figure 5.1c, for the simplicity of analysis.

a) Ideal b) Real - with oh-

mic losses

c) Equivalent parallel

circuit

d) LC tank with parallel nega-

tive resistance

Figure 5.1: LC tank circuit

The losses in an LC tank define the quality of the oscillator. Considering the circuit in Figure 5.1c, where a finite resistance is taken into account, once the energy is inject into the circuit the oscillation starts up and will tend to decay due to the losses in Rp. This leads to the definition of the Quality factor (Q) [71], [75], the most important parameter of an LC tank. The lower the energy dissipated, the better is the LC tank performance.

DissipatedPowerAverageStoredEnergyfQ 02π=

(5.1)

As aforementioned, when a signal is injected into an LC oscillator, it starts oscillating and then the oscillation will die due to the circuit losses. Generally, the active circuit (VCO transistors) compensates for this loss by providing a negative resistance (negative conduc-tance) that cancels out the positive conductance of the tank as represented in Figure 5.1d. In the LC tank with a feedback circuit, if the negative resistance is greater than the positive par-allel resistance, then when an oscillation starts, its amplitude will grow with time. Moreover, and according to Barkhausen criteria, if the overall resistance of the circuit is negative, then the oscillation amplitude will continue to grow indefinitely [5]. However, oscillation amplitude will be limited either by the power supply or current limits, or even by some nonlinearities of the circuit, guiding the oscillation amplitude to a finite value. Nevertheless, this negative resis-tance system reduces the losses in the circuit, consequently attaining a better quality factor (Q).

In an LC-tank oscillator, by using a capacitance C depending on a DC tuning voltage, the circuit becomes a voltage-controlled oscillator (VCO), with a centre frequency

LCf

π21

0 =

(5.2)

and the frequency tuning range of the VCO is given by


101

min

max

min

max

CC

ffftuning ==

(5.3)

where Cmax and Cmin are the maximum and minimum capacitance obtainable by the tunable capacitor (varactor).

The energy conservation theory states that the maximum energy stored in the inductor should be equal to the maximum energy stored in the varactor. That leads to

2max

2max CULI =

(5.4)

where Imax is the maximum current through the inductor and Umax is the peak voltage applied to the varactor [76]. The power dissipation is given by

2max

2max 2

121 U

LRCRIPdissip ==

(5.5)

which can be written using (5.2), yielding

( )( )

.2

1212

21 2

max220

2max

20 U

LR

fRCUfPdissip π

π ==

(5.6)

The LC-tank power dissipation at a given frequency is inversely proportional to the inductance by a power of two (L2). Thus, to reduce power consumption large inductors are needed. Yet this will lead to an increase in the implementation area, as the inductor number (n) of wind-

ings increase, since 2nL ∝ even with nR ∝ .

We may therefore conclude that the quality factor (Q) of the tank circuit has great im-pact on the main characteristics of oscillator, such as the output voltage swing and power dis-sipation. The oscillation amplitude is proportional to the impedance of the resonator and the current delivered to the tank circuit [14]. While high output voltage swing is obtained with high currents, on the other hand low power consumption, means low current delivered to the circuit, for a fixed supply voltage. In practical applications, usually there is a specification for the supply voltage and current or power consumption. Additionally, it is desired to achieve high output voltage swing, since the oscillator drives other circuits, by generating a reference frequency, such as up/down converts or frequency dividers, where circuit linearity and noise contributions are strongly linked with the input signal. From a practical design point of view, an oscillator is designed to achieve an output voltage swing between half and peak-to-peak, with respect to the supply voltage. The total power needed to reach such output swing, is strongly dependent on the resonator quality factor (Q). Concerning low power oscillators, for several decades off-chip resonators were widely used, since they offers quality factors typically ten times higher when compared with full on-chip resonators. The main contributor for such low quality factor is the on-chip inductor.


102

However, off-chip inductors, albeit having outstanding performance with high quality fac-tors, are not compliant with the rising demand to low-cost fully integrated systems. The drive towards full circuit integration has revived interest in CMOS processes where the cost savings inherent to a completely integrated system have encouraged circuit design at frequencies which were not considered viable before.

Integrated planar inductors on silicon are known for their poor performance and their subsequent impact on circuit efficiency at high frequencies. This limitation is due to the large effect the technology parasitics have on the small value of inductance usually required. None-theless, the design of a planar inductor is a challenging problem since there is the need to accurately model inductor’s electrical and magnetic properties, which involves many correlated parameters, encompassing both geometrical and technological parameters. As a result, signifi-cant effort has been employed in investigating silicon planar inductors, their associated mod-els, as well as methods of improving their performance.

The need for designing integrated inductors with specifications that push the technology to its limits associated with the complexity of their design has motivated the development of optimization-based techniques [77], [78] and [79]. In these approaches, however, continu-ous variable optimization techniques are employed and constraints are considered only on the bounding values for the inductor layout parameters. Although, the inductor design is not com-pliant with continuous variable optimization as part of the design parameters has a discrete nature. Thus, when technology-constrains regarding the discrete nature of the variables is for-gotten in the design process, it may yield sub-optimum solutions where the correlation of the parameters obtained is not granted. This technology limitation underlines the need for optimi-zation strategies regarding the inductor design.

In this chapter an optimization-based design of the LC-tank is proposed. Integrated and planar inductors are widely used in LC-tank oscillators due to the simplicity of fabrication in standard processes in spite of their low quality factor (Q) and large area of implementation. On the other hand, the varactor should also be carefully designed since it gives the tunable characteristic to the resonator. Moreover, as the varactor is implemented in standard CMOS technology, its capacitance as well as the tuning range is dependent on transistor size.

In the following sections, a brief description the different optimization methodologies ap-plied to circuit design is offered. A special attention will be given to the optimization-based design of the inductor and the varactor. The proposed optimization methodology was imple-mented in Matlab, and design solutions are obtained by means of evolutionary algorithms, namely the Genetic Algorithms (GA).


103

5.2 Optimization Approaches

Analog components play an important role in integrated circuits, since they make the bridge between the off-chip analog environment and the on-chip digital signal processing. Yet, analog circuits are difficult to design and reluctant to design automation. Traditionally, these circuits range from a few transistors to around hundred(s) of transistors and were designed based on numerical simulation with SPICE-like engines for the evaluation of a circuit’s per-formance. But analog circuits on modern ICs are more complex and manual sizing of analog blocks through SPICE-like simulation is a bottleneck and governs the time-to-market. Thus, more efficient sizing methodologies have to be entered [80].

The technology evolution is guided by digital circuits, as they are more and more char-acterized by lower voltage supply, lower power consumption and reduced area. Therefore, an accurate prediction of the analog counterpart behaviour is mandatory as technology is scaled. Circuit sizing has been considered as an optimization problem that aims for better designs and shorter time to market [81].

The design of a circuit through an optimization-based methodology can follow two dif-ferent paths: simulation or equation-based optimization. In the simulation-based optimization the circuit design relies on a SPICE-like simulator, considered as a black box evaluator that receives as input the circuit parameters and returns the circuit performance values. During the design process, the interaction with the simulator is done through an optimization algorithm that assesses if the circuit is compliant with the design specifications. On the other hand, the designer also has access to circuit equations to estimate its behaviour. These equations can be derived in very different ways: by symbolically analysing the circuit or by means of soft-ware that automatically obtain those equations. However, the equation-based optimization loses accuracy when compared with simulation-based optimization, as the assumed device behaviour is somehow estimated through some approximations during the circuit analysis. In Table 5.1 a short comparison of both optimization techniques, regarding their main character-istics, is offered [82], [83].

Table 5.1: Simulation and equation-based optimization

Simulation-based Optim. Equation-based Optim.

Optim. Methodology

SPICE-like engine evaluation Equation-based evaluation

Single or multi-objectives Single or multi-constraints

Optim. Algorithm Stochastic and non-stochastic / deterministic and non-deterministic

(Simulated Annealing, Evolutionary Algorithms, ...)


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As shown in Table 5.1, both the simulation-based and equation-based optimization just differs in the way circuit performance is evaluated. Similarly to what was presented in Table 5.1, a comparison between both optimization approaches, regarding several metrics, such as accuracy, computation time or robustness, is given in Table 5.2 [81].

Table 5.2: Comparison between simulation and equation-based approaches

Simulation-based Optim. Equation-based Optim.

Accuracy

Good accuracy as SPICE-like en-gine is invoked in the optim loop;

Takes into account nonlinearities;

Possible inaccuracy when used in stochastic optim;

Possible inaccuracy during equations

extraction process; Although, good accuracy on the

given models;

Comp. Time

Almost no time need for the problem

formulation; High time of optimization since

simulator is invoked in the optim

loop;

High time in problem formulation and

obtaining circuit equations; Very fast when computing circuit

behaviour;

Effort Little effort needed to write down the

simulator netlist;

Strong effort when writing the circuit

equations:

Robustness

Need extra number of simulations to

evaluate the robustness of the solu-tion found;

Fast to evaluate the robustness of

the solution, regarding parameters variation;

In Table 5.2 is done a comparison between simulation-based and equation-based opti-mization regarding some metrics that usually are used to decide what type of optimization ap-proach is better for a specific problem. By analysing the advantages and drawbacks of each approach, it is possible to state that equation-based optimization is preferable to solve prob-lems with large number of variables, although high effort and time is put on the problem for-mulation side, but the evaluation of the robustness is performed in short time. On the other hand, simulation-based optimization, due to the high time needed to evaluate each candidate solution of the problem under analysis, is not appropriated for large problems. Some tech-niques to divide the problem in multi sub-problems are used trying to reduce the simulation time, as each sub-problem deals with a smaller number of variables. The main advantage of this strategy is the small amount of effort and time needed to formulate the problem as well as to prepare a netlist for the simulation engine. If the circuit robustness is a main issue in the optimization process, simulation-based approach will greatly increase the optimization time.

Circuit sizing by means of equation-based optimization are known by the need for high effort and time in both to write the equations that estimates the circuit behaviour and to setup


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the optimization problem. Yet, the circuit sizing optimization is considered to be achieved in a reasonable time, where the accuracy of the results relies on the precision of the device mod-els. Moreover, if robustness analysis is desired, equation-based optimization handles a very high number of variation parameters without compromising the total design time. Additionally, if the model equations are based on technological parameters, it is suitable to be used as tech-nology scales down. By what was aforementioned, the equation-based optimization will be adopted in this work.

5.2.1 Optimization Methods

Several optimization methods exist and can be categorized as shown in Figure 5.2.

Optimization Methods

Classical Methods

Enumerative methods

Stochastic Methods

LinearProgramming & Others

Non-LinearProgramming

Fibonacci, Newtow, GreedyDirect

Indirect

Dynamic Prog., Branch &BoundGuided

Non Guided Backtracking

Solves non-linear set of equations, setting the gradient of the obj function to zero

Figure 5.2: Optimization methods

Linear Programming intends to obtain optimal solution to problems which must be de-scribed by a set of linear equations, therefore, require a priori knowledge of the problem. Moreover, the objective functions must be represented as linear relationships. Among the non-linear programming optimization methods can be found three large groups: classical, enumera-tive and stochastic. Classical search method uses deterministic approach to come across the best solution. These methods also require previous knowledge regarding the gradients or higher order derivatives. Although, in many analog circuit sizing problems, some desired in-formation is not possible to obtain, which make this kind of deterministic algorithms inappro-priate for such kind of problems. The enumerative method is considered an exhaustive search methodology, as it goes through every point of the search space. At each point, all solutions


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are generated and evaluated in order to find best solution. For optimization problems that deals with a large number of variables, this type of search method is timely prohibitive.

Stochastic search methodology intentionally introduces randomness into the search process, which means that the search party moves from one position to another in a non-deterministic way. This randomness aims to avoid the search engine of getting trapped in lo-cal optima solutions. The main advantage of this search technique is that there is no need of previous information regarding the problem being optimized. Therefore, this is the proper search method to be used in the optimization problem under consideration in this work. As one of the most used search method, a large range of the different stochastic approaches has been proposed, as depicted in Figure 5.3.

Stochastic Methods

Non-GuidedGuided Las Vegas

Hopfield, Kohmen Maps, ... Neural Networks EVOLUTIONARY

ALGORITHMSGenetic Programming, Evolutionary Strategies, Evolutionary Programming

GENETIC ALGORITHMS

Sequential GasParallel GAs Generational, Steady-State, Messy

Automatic Parallelim

One PopulationParallel Evaluation + Crossover + Mutation

CoarseGrain

FineGrain

Particle Swarm Opt (PSO)

Tabu Search, Simulated Aneealing

Figure 5.3: Stochastic search methods

Among several stochastic search methods, the evolutionary algorithms use evolution of species as an inspiration for solving optimization problems that requires searching through a huge number of possibilities for solutions. In typical engineering problems, finding a solution means trying to find the best among other possible solutions. For this reason, evolutionary algorithms will be considered in this work, and presented in the next subsection.

5.2.1.1 Evolutionary Algorithms

From the very first days computers were applied not only to complex calculus proce-dures, but also to modeling the brain, to mimic the human behaviour or to simulate biological evolution that a new field has raised in the computation community, the so called computation search methodologies. The first steps were done through the field of neural networks, then into machine learning, and finally into what is known as evolutionary computation [84].


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Since the early 1960s several researchers had started working on the development of evolution-inspired algorithms for problems optimization. More recently, there has been pro-posed numerous techniques that combine various evolutionary computation methods and the boundaries between, evolution strategies, evolutionary programming, and other evolutionary approaches have broken down and all of them fit under the umbrella of evolutionary algo-rithms. Evolutionary algorithms are said to be suitable for computational problems that require complex solutions that are difficult to program by hand.

Despite some lack of explanation regarding the details of biological evolution, there are some interpretations which are supported by experimental observation [85]:

− Evolution is a process operating over chromosomes rather than over organisms;

− Natural selection is the mechanism that relates chromosomes with the efficiency of the entity they represent;

− The evolutionary process takes place during the reproduction phase.

Based on the three mentioned features, the development of evolutionary algorithms (EA) took place. An EA is an iterative and stochastic process that operates on a set of individuals, which forms a population, where each individual represents a probable solution to the problem under consideration. Every single individual that belongs to the population is evaluated by means of a fitness function, and its value represents a measure of its quality, regarding the problem in analysis. This value that characterizes the individual contains the information used by the algorithm, to go into the next step in the search procedure.

Among the evolutionary techniques, there are two of them that have a prominent place: the genetic algorithms (GA) and the particle swarm optimization (PSO).

A. Genetic Algorithms

As before mentioned, genetic algorithms belong to the class of stochastic search optimi-zation methods. The GA use only the results obtained through the fitness function in the search space process - search a population of points in parallel instead of a single point, thus making results less sensitive to the point chosen - in order to go towards the best solution. Continuity or discontinuity of the problem functions is neither required nor used in calculations of the algorithm loop, Figure 5.4. This feature makes the GA very general and suitable for all kind of problems: discrete, continuous, non-differentiable, or even mixed search spaces. Fur-thermore, GAs do not require derivative information or previous knowledge, as well as the algorithm determines global optimum solutions, avoiding getting trapped in local maxi-mum/minimum, as frequently happen with continuous variable optimization algorithms [86].


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Generate Initial Population

EvaluateFitness Func.

Optimization criteria met ?

Best Individualsfound

Selection

Crossover

Generation Popul.Mutation

No

Yes

Figure 5.4: Genetic Algorithm procedure flowchart

B. Particle Swarm Optimization

Particle Swarm Optimization is a population based metaheuristic inspired by social be-haviour of bird flocking or fish schooling [87]. In contrast to GA, PSO algorithm has no evo-lution operators (but is commonly included in the evolutionary algorithms group). Each poten-tial solution in the problem is called particle and the population of particles is called swarm. During the exploration process in the design space, each particle is characterized by its posi-tion and velocity. During the swarm fly, the next position of each particle is influenced by the position and velocity of the previous best encountered solution. The flowchart that describes the PSO algorithm is detailed in Figure 5.5. As for the GA, also the PSO is suitable for dif-ferent problems nature.

Generate Initial Population

EvaluateFitness Func.

Optimization criteria met ?

Best Individualsfound

Update particles velocity

Update particles position

Update local bests and global best

No

Yes

Figure 5.5: Particle Swarm Optimization procedure flowchart

PSO is similar to the Genetic Algorithm (GA) in the sense that they are both popula-tion-based search approaches and that they both depend on information sharing among their population members to enhance their search processes using a combination of deterministic and probabilistic rules. It is common word-of-mouth statement that although PSO and the GA on average yield the same quality regarding the solution found, PSO is more computationally efficient, meaning that uses less number of function evaluations, than the GA.

In [88] a performance test to both algorithms was carried out and conclusion achieve. The results of the several tests support the hypothesis that while both PSO and the GA obtain high quality solutions, around 99%, the computational effort required by PSO is less than the effort required to arrive at the same high quality solutions by the GA. Moreover, the same set of tests shows that the difference in computational effort between PSO and the GA is problem


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dependent. The PSO takes advantage regarding the GA in computational efficiency when used to solve unconstrained nonlinear problems with continuous design variables. On the other hand GA outperforms the PSO when applied to constrained nonlinear problems with continu-ous or discrete design variables. For this reason GA is the chosen search algorithm to be used in this work.

Notwithstanding all the merits assigned to and GA, there are two main drawbacks, which are:

− Usually GA requires a large amount of calculations for even small complex problems, or if the fitness function itself involves a huge number of calculations;

− There is no absolute guarantee that the best solution is achieved.

However, if to overcome the first drawback a technology solution is needed, such as faster computers or a parallel computation strategy, for the second, the approach can be either the use of a massive population in order to search more area of the search space in each itera-tion, or execute the algorithm several times as a metric of its robustness of convergence.

5.3 Integrated Inductor Optimization-Based Design

Until the end of the last century, high performance transceivers used off-chip passive elements due to their high quality factor (Q) [48]. However, off-chip inductors, albeit having outstanding performance with high quality factors, are not compliant with the rising demand to low-cost fully integrated systems. The drive towards full circuit integration has revived interest in CMOS processes where the cost savings inherent to a completely integrated system have encouraged circuit design at frequencies which were not considered viable before.

Integrated planar inductors on silicon are known for their poor performance and their subsequent impact on circuit efficacy at high frequencies. This limitation is due to the large effect the technology parasitics have on the small value of inductance usually required. As a result, significant effort has been employed in investigating silicon planar inductors, their asso-ciated models, as well as methods of improving their performance.

Designing a spiral inductor involves the determination of multiple correlated variables, encompassing both geometrical and technological parameters. The methodology usually adopted by analogue designers based on iterative simulations is a time prohibitive approach for this kind of devices since electromagnetic simulations are a time consuming process. To overcome this problem, designers adopt methodologies based on either pre-characterized in-ductor designs or ad-hoc techniques [7]. Other methodologies rely on fine-tune s parameter based models or even empirical models. Yet, the rapid technology evolution, makes these models easily obsolete, thus increasing the need for physically based models. Previous at-


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tempts at modelling integrated inductors have concentrated on the simple π-model that does not account for all the high frequency and parasitic effects. The necessity for overcoming the limitations mentioned above motivated the development of the double π-model, as was high-lighted in Chapter 2.

In the following subsections, the methodology for the optimization based design of RF integrated inductors is described, and then, several working examples will be presented. The validity of the results achieve with the proposed methodology is done by comparison with re-sults obtained through electromagnetic simulation performed with ASITIC.

5.3.1 Optimization Methodology for Inductor Design

Integrated inductors may be used in different analogue blocks such as LNAs or VCOs. Depending on the application several characteristics may be used for evaluating the quality of the inductor design, such as the inductor quality factor (Q), the accuracy of its inductance value or the self-resonant frequency. All these characteristics are influenced by the spiral in-ductor geometrical parameters as well as the technological parameters and constraints.

The geometrical parameters, as illustrated in Figure 5.6, comprise the inductor track width (w), track-to-track spacing (s), number of turns (n), inductor shape (Nside), as well as internal and external diameter (din, dout). Concerning the technological process, the parameters that mainly influence the inductor are [21]: metal thickness (t) and resistivity (ρ); dielectric thickness and permittivity/losses; substrate structure and conductivity (σ); and the permeabil-ity of each material (ε). The influence of these parameters in the inductor quality factor as well as its inductance value has been reported in literature [54], [89].

Figure 5.6: Layout of a square inductor

Some trade-offs regarding the geometric and technological parameters (and parasitics) of the inductor can be easily understood. Inductors with large track width, have lower resis-tance and consequently higher Q. On the other hand an increase in the area shared by the spiral and the substrate, increases the capacitive coupling, yielding a lower frequency for maximum quality factor (Q). For a fixed area, the shape that has the shortest perimeter is the circle. This means that, with a circular configuration, the highest inductance is obtained, yield-ing higher quality factor (Q). Yet, some technologies show limitations on the feasibility of cir-


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cular inductors [90]. Mutual inductance between track segments is influenced by their angle of intersection, length and distance, thus influencing the inductance and the quality factor.

As the design of a fully integrated spiral inductor for RFIC entails the calculus of a sig-nificant number of geometric parameters, all of them affecting the performance of the inductor in different ways, several methods and approaches have been explored, as mentioned before.

5.3.1.1 Main characteristics of the inductor design

The methodology adopted aims to achieve a technology/topology-aware solution. Also to be accounted for is the discrete nature of the design variables, as well as, the correlation between them. The design concerns the evaluation of four independent parameters, namely the track width (w), the number of turns (n), inductor shape (Nside), and the internal diameter (din). Regarding the number of turns (n), a minimum value of 1.5 was considered. Subse-quent values are obtained with unitary increment, i.e.,

[[ ...,5.3,5.2,5.1∈n

(5.7)

Due to the approximation considered to calculate the inductance value for low frequen-cies (Ldc), the shape of the inductor must account for square, hexagonal and octagonal to-pologies. Regarding the technological constraints, minimum values for the track width (w), for the track-to-track spacing (s), and for the internal diameter (din), were accounted for. Tech-nology-dependent minimum increment values for these layout parameters were also consid-ered. Finally the correlation between the layout parameters defined by (5.8) is considered, as way of including heuristic design rules. This rules aim to reduce the parasitic phenomena re-garding the proximity effect due to the inner turns [70]. As the ratio between din and dout de-creases, the coupling capacitance to the substrate grows.

wddd

in

outin

58.02.0

≥≤≤

(5.8)

If we define Cost(n, din, w, Nside) and L(n, din, w, Nside) as the cost function and the in-ductance of the spiral, and Lexp and δ the targeting inductance value and the tolerance al-lowed for the inductance to deviate from the targeting value, the optimization problem is for-mulated as the minimization of Cost(n, din, w, s) subject to

( )( ) ( ) ( )

[ ][ ][ ]

[ ]8,6,4::

::::

1,,,1,,,

maxmin

maxmin

maxmin

expexp

∈∈

∈∈

⋅+≤≤⋅−

side

w

indinin

n

sidein

sidein

Nwstepww

dstepddnstepnn

LNwdnLLtoSubjectNwdnCostMinimize

in

δδ

(5.9)


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Concerning the cost function three different scenarios are available yielding either the minimization of the tolerance, δ, the minimization of the device area, dout, or the maximization of the quality factor, Q, for a predefined frequency of operation and a maximum output diame-ter, dout.

5.3.1.2 Genetic Algorithms

During the last years Genetic Algorithms (GAs) have been widely used in circuit design, although it application has deal with continuous variables optimization [91], [92]. In this work a modified GA tool for the optimization-based design of spiral inductors is introduced. In this tool the solution is obtained considering user-defined constraints in the design, reflecting a discretization of the variable values according to the technology used. Further constraints im-posing bounds on the ratio between design variables are also accounted for as a way of sup-porting design heuristics [70]. Figure 5.7 gives a general idea of the followed optimization design approach.

Optimized parameters

Objec

tive

func

tions M

odelsTechnology

parametersOp

timiza

tion

crite

ria

Specifications

CandidatesSelection

Objective functionsEvaluation

Figure 5.7: General architecture for an optimization design approach

As aforementioned genetic algorithms (GA) are a stochastic search method that mimics the natural biological evolution, operating on a population of potential solutions, applying the principle of survival of the fittest to produce better and better approximations to a solution. So, GA can be applied to any problem that can be formulated as function optimization problems.

The optimization tool developed was implemented with the Matlab GA toolbox [93]. Since this toolbox shows several limitations for discrete optimization problems, where each variable has a predefined step-size, three functions were developed. The flowchart showing the process of modified GA (MGA) is represented in Figure 5.8, where the additional func-tions, are shown with a dark (green) background.

For the inductor design, the MGA procedure starts with the creation of the initial popu-lation, where each individual is composed by the four variables (n, din, w, Nside), representing


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the layout geometry parameters. The initial population is randomly created, but the individual’s genes must lay within the variable boundaries. As illustrated in Figure 5.8 an alternative func-tion for creating an integer-valued population is used (written below).

SpecificationsTech. parameters

Create Initial Population

Create Initial Population

Matlab GA Tbx

Evaluate Fitness Func.

Mapping Integer to Real Values

Optimal or Good Solution Found?

Selection for Reproduction

IntegerMutation

Create New Population

Matlab GA Tbx

Stop !

Max Num of Iteration orFitness Func. Less than

Func, Tolerance

Figure 5.8: Basic Genetic Algorithm Optimization Flowchart

function Population = integer_pop(GenomeLength,FitnessFcn,options) totalpopulation = sum(options.PopulationSize); range = options.PopInitRange; lowerBound= range(1,:); cluster = range(2,:) - lowerBound; % ROUND function guarantee that individuals are integers Population = repmat(lowerBound,totalpopulation,1) + ... round(repmat(cluster,totalpopulation,1) .* rand(totalpopulation,GenomeLength)); % End of function population

The population is converted to real values and then evaluated through the objective function. In this function each individual is evaluated according to the constraints imposed and if it is not compliant, a penalty is applied so that it shows a very low probability of being elected for the next population. The next step accounts for the generation of a new popula-tion. Here selection and reproduction functions are used. For the selection the roulette wheel method is chosen. Afterwards, reproduction (or mutation) is made. Due to the difficulty of Matlab in dealing with real-valued population with predefined step-size, a mutation function


114

was defined, allowing the creation of a new population of integer-valued individuals (shown beneath). The algorithm stops here, if termination conditions are met.

function mutationChildren = integer_mutation(parents,options,... GenomeLength,FitnessFcn,state,thisScore,thisPopulation)

scale = 1.0; scale = scale * state.Generation/options.Generations; range = options.PopInitRange; lowerBound = range(1,:); upperBound = range(2,:); scale = scale * (upperBound - lowerBound); mutationPop = length(parents); mutationChildren = repmat(lowerBound,mutationPop,1) ... + round(repmat(scale,mutationPop,1) .* ... rand(mutationPop,GenomeLength)); % End of function mutationChildren

5.3.2 Inductor Design

The results in this section highlight the ability of the proposed methodology, combining the inductor simple/double π-model and a genetic algorithm optimization procedure, to achieve optimal design of spiral inductors. The ASITIC simulator must be seen as a first ap-proximation step in the design of an inductor, due to some limitations that were reported in related bibliography [70]. Among the limitation, the lack of account for the magnetic induced current effects in the substrate and the proximity effects between metallic layers of the induc-tor. Despite these limitations, the results here presented are validated against results obtained through ASITIC simulations.

In this section design examples for UMC130 technology are addressed, where the tech-nological and physical parameters are shown in Table 5.3. The determination of the layout parameters is done according to the constraints represented in Table 5.4.

Table 5.3: Physical parameters of inductor design

Parameter Value

Metal Thickness 2.8 µm

Space between turns 1.5 / 2.5 µm Sheet Resistance 10 mΩ/square

Oxide Thickness 5.42 µm

Oxide Thickness between spi-ral and underpass

0.40 µm

Oxide Permittivity (εr) 4.0

Substrate Thickness 700 µm Substrate Permittivity (εr) 11.9

Substrate Resistivity 28 Ω.cm


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Table 5.4: Design constraints

Parameter Min Step Max

w (µm) 5.0 0.25 50.0

din (µm) 20.0 0.25 250.0 n 1.5 1.0 15.5

Nside Square (4) / Hexagonal (6) / Octagonal (8)

5.3.2.1 Continuous vs Discrete Variable Optimization

The design of integrated inductors is a discrete-variable problem. However, in some published works, continuous variable optimization techniques are considered and constraints are taken into account only on the maximum/minimum values for the inductor layout parame-ters. Technology-constrains regarding the discrete nature of the variables is dealt in a subse-quent procedure where the layout parameters obtained from simulation are rounded to the most convenient technology feasible discrete value [78], [79], [94]. In this subsection it will be shown that results obtained from continuous variable optimization approach, where in the end a parameters discretization is made, achieves to higher error when compared with a dis-crete variable optimization. For the implementation of the optimization approaches mentioned, the two methodologies described next were considered. Both procedures were implemented in Matlab with the optimization toolbox. For the simplicity of the analytical model used, the sim-ple π-model was considered.

C. Continuous Variable Methodology

In this methodology the technology/topology-aware solution is obtained in two steps. In this first step, continuous variables were used for the optimization of the layout design pa-rameters. The second step aims at generating a final solution respecting the granularity of the layout parameter values needed for granting the feasibility of the design.

Besides the constraints defined in (5.8) further technological/topological constraints were defined as

( )( ) ( ) ( )

84

1,,,1,,,

maxmin

maxmin

maxmin

expexp

≤≤≤≤

≤≤≤≤

⋅+≤≤⋅−

side

ininin

sidein

sidein

Nwwwddd

nnnLNwdnLLtoSubject

NwdnCostMinimizeδδ

(5.10)

In the second step, the solution obtained in the previous step is used. For each of the layout parameters generated, the two neighbours obtained either by rounding-up and round-


116

ing-down the given value, to the next technology-possible values, are elected. A table with all the combinations of the previously elected values for each parameter is generated. For each table entry the initial cost function is computed and the best value is chosen.

D. Discrete Variable Methodology

For this procedure an additional Matlab function, where the Branch-and-Bound algorithm is implemented, is used for the discretization of the variables. The optimization procedure is formulated considering the constraints given by (5.8) and (5.9) and technology/topology aware results are provided in a single design step.

E. Working Examples

The design of 7.0 nH inductor for an operation frequency of 0.8 GHz is addressed. Two working examples considering an integrated spiral inductor, for minimum inductance toler-ance, δ, and for maximum quality factor, Q, are presented. In both working examples the technological parameters shown in Table 5.3 and Table 5.4 are used.

Example 1

In this example the inductor layout parameters which minimize the tolerance, δ, are computed. Considering a continuous variable optimization, the results obtained are shown in Table 5.5.

Table 5.5: Optimization results for minimum tolerance

w (µm) din (µm) n Nside Ltool (nH) δ (%Error) Qtool

5.0 36.6 8.35 4 7.00 0.0 2.19

For the layout parameters obtained, the technology feasible neighbouring layout pa-rameters represented in Table 5.6 were considered. Since the values for w and Nside are tech-nology feasible, only neighbouring points for n and din were considered. For each of these points, the corresponding inductance is represented in the same Table, as well as the relative error to the envisaged inductance value. As we may easily conclude, the best solution ob-tained is for w=5 µm, Nsides=4, n=8.5 and din=36.5µm, but which leads to an inductance value with a relative error of 3.9%.

Table 5.6: Final inductance and % error for several solutions

din=36.5µm din=36.75µm L (nH) %Error L (nH) %Error

n=8.0 6.30 10.0 6.34 9.4 n=8.5 7.27 3.9 7.30 4.3


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Considering the discrete-variable optimization methodology proposed, the values ob-tained are represented in first row of Table 5.7. Also in the same table, the layout parameters obtained with the continuous methodology are represented. As we may easily conclude, the discrete-variable optimization methodology yields to a much better result.

Table 5.7: Final results for minimum tolerance with discrete-variable optimization

Methodology w (µm) din (µm) n Nside Ltool (nH) %Error Qtool

Discrete-Variable 5.5 41.0 8.0 4 6.99 1.4e-3 2.35

Continuous-Variable 5.0 36.5 8.5 4 7.27 3.9 2.21

The validity of these results was checked against simulation with ASITIC yielding results shown in Table 5.8. From this comparison we may conclude that a solution is obtained with an error of less than 2.5% relatively to the results obtained from simulation with ASITIC.

Table 5.8: Comparison of results between evaluated and simulated

Ltool (nH) LAsitic (nH) %ErrorL Qtool QAsitic %ErrorQ 6.99 6.90 1.30 2.35 2.30 2.17

Example 2

In this example the inductor layout parameters that maximize the quality factor for a maximum inductance tolerance of 5% are computed. Considering a continuous variable optimi-zation, the results obtained are shown in Table 5.9.

Table 5.9: Optimization results for maximum Q

w (µm) din (µm) n Nside Ltool (nH) %Error Qtool

50.0 250.0 3.88 7.98 7.35 5 11.84

For the layout parameters obtained, the technology feasible neighbouring layout pa-rameters represented in Table 5.10 were considered. Since the values for w and din are tech-nology feasible, only neighbouring points for n and Nside were considered. For each of these points, the corresponding inductance and quality factor, Q, are represented in the same table as well as the relative error to the envisaged inductance value. As we may easily conclude, the best solution obtained, considering a maximum quality factor and a tolerance as close to 5% as possible, is for w=50µm, Nsides=6, n=4.0 and din=250µm. This solution, however, fails in maximum allowed tolerance for inductance value since it shows a magnitude of 11.85%

Table 5.10: Final inductance and % error for several solutions

Nside=6 Nside=8 Q L (nH) %Error Q L (nH) %Error

n=3.5 10.60 5.93 15.30 11.19 5.99 14.5 n=4.0 11.55 7.83 11.85 12.20 7.91 13.0


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Considering the discrete-variable optimization methodology proposed, the values ob-tained are represented in the first row of Table 5.11. Also in the same table, the layout pa-rameters obtained with the continuous methodology are represented in the second row. As we may easily conclude, with the discrete-variable optimization methodology, we obtain techno-logical valid layout parameters for an inductance value within the given tolerance, and with a quality factor of 11.3. The first methodology fails to generate an inductance value within the envisaged maximum tolerance.

Table 5.11: Final results for minimum tolerance with discrete-variable optimization

Methodology Qtool w (µm) din (µm) n Nside Ltool (nH) %Error Discrete-Variable 11.30 46.75 234.5 4.0 8 7.35 5.0

Continuous-Variable 11.55 50.00 250.0 4.0 6 7.83 11.85

The validity of these results was checked against simulation with ASITIC yielding results shown in Table 5.12. From this comparison we may conclude that a solution is obtained with an error of less than 5% relatively to the results obtained from simulation with ASITIC.

Table 5.12: Comparison of results between evaluated and simulated

Ltool (nH) LAsitic (nH) %ErrorL Qtool QAsitic %ErrorQ 7.35 7.14 2.94 11.30 10.79 4.72

In these examples a comparison between the discrete-variable optimization and using continuous optimization followed by a technology-aware discretization of the results is per-formed. In both examples the discrete–variable optimization proved to be better. Moreover, in the second example, maximize Q, the solution obtained through the continuous optimization approach is not compliant with the design specifications.

5.3.2.2 Discrete-Variable Optimization Examples

In this subsection, the design of a 5.0 nH inductor and a 7.0 nH inductor for an oper-ating frequencies of 0.7, 1.0 and 1.5 GHz for UMC130 technology is addressed, where the technological and physical parameters are shown in Table 5.3. The determination of the lay-out parameters is done according to the constraints represented in Table 5.4. For this set of examples, a space between tracks of 2.5 µm is assumed. Although, the inductor shape is set to a square inductor, the optimization algorithm is prepared to account for different inductor shapes.

For each of the above cases, three different objective functions are addressed. In ex-ample A, the inductor layout parameters minimizing the tolerance, δ, are computed; example B deals with designing an inductor with the smallest device area. Finally, in example C, an


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inductor with maximum quality factor, given a maximum output diameter of 200 µm in the case of the 5 nH inductor (and 250 µm for the 7 nH inductor), is obtained. In examples B and C the tolerance, δ, is an additional constraint, with maximum value of 2.5%. The results obtained are presented in Table 5.13 and Table 5.14. The validity of these results was checked against simulation with ASITIC yielding results also shown in both tables.

Table 5.13: Optimization results for a square inductor of 5 nH (Dout max of 200 µm) and its comparison with ASITIC simulations

Frequency 0.7 (GHz) 1.0 (GHz) 1.5 (GHz)

Optim. A B C A B C A B C

w (µm) 7.50 5.00 9.25 6.75 5.25 8.75 5.00 5.50 10.75

din (µm) 68.25 46.25 66.75 42.25 45.50 103.50 99.00 64.75 54.75

n 5.5 6.5 5.5 6.5 6.5 4.5 4.5 5.5 5.5

dout (µm) 173.25 138.25 191.00 157.50 141.25 199.75 161.50 147.75 195.50

Ltool (nH) 4.98 4.90 5.04 4.99 4.97 5.05 5.01 4.90 4.97

δ (%) 0.3 1.9 0.9 0.2 0.6 1.0 0.1 2.0 0.6

LAsitic (nH) 4.86 4.77 4.93 4.82 4.79 4.84 4.71 4.59 4.51

Error (%) 2.5 2.8 2.3 3.6 3.8 4.3 6.3 6.7 10.2

Qtool 5.50 4.10 6.32 6.72 5.76 8.15 7.54 7.99 10.78

QAsitic 5.01 3.68 5.71 6.22 5.29 7.77 7.63 7.88 10.83

Error (%) 9.9 11.4 10.6 8.0 8.8 4.9 1.1 1.4 0.5

Table 5.14: Optimization results for a square inductor of 7 nH (Dout max of 250 µm) and its comparison with ASITIC simulations

Frequency 0.7 (GHz) 1.0 (GHz) 1.5 (GHz)

Optim. A B C A B C A B C w (µm) 7.50 5.00 12.50 10.00 5.50 11.50 8.75 5.75 11.75

din (µm) 65.00 46.75 89.75 89.50 43.25 86.75 70.25 38.00 120.50

n 6.5 7.5 5.5 5.5 7.5 5.5 6.5 7.5 4.5

dout (µm) 190.00 154.25 249.75 222.00 158.25 235.75 205.00 156.75 243.75

Ltool (nH) 6.99 6.90 6.94 6.99 6.87 7.01 7.03 6.86 6.90

δ (%) 0.2 1.4 0.8 0.1 1.8 0.1 0.5 2.0 1.4

LAsitic (nH) 6.75 6.69 6.64 6.49 6.56 6.44 7.18 6.27 5.84

Error (%) 3.5 3.2 4.6 7.8 4.8 8.9 2.0 9.4 18.2

Qtool 5.93 4.47 8.13 8.94 6.25 9.49 9.31 7.93 10.44

QAsitic 5.52 4.11 7.63 8.89 5.97 9.48 8.81 8.17 12.02

Error (%) 7.5 8.9 6.6 0.6 4.7 0.1 5.7 2.9 13.1

For the inductor obtained in the first row of Table 5.13, the corresponding inductance value as well as quality factor over a frequency range up to 5 GHz is depicted in Figure 5.9.


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Also in this figure, the dashed line marks the point at which the quality factor reaches its maximum. The area on the left, indicated as low, is an area where the quality factor is mainly influenced by the DC resistance, skin and proximity effects and the magnetic induced losses. On the other side of the dashed line, besides the previous effects, the quality factor is also influenced by the electrical substrate coupling to the substrate [70].

Figure 5.9: Inductance and quality factor for the designed Inductor

One of the less positive aspects of using evolutionary algorithms, applied to such prob-lems as inductors design, is that the optimization procedure merely gives a single set of in-ductor parameters, and no information regarding other combinations in the neighbourhood is given. In some situations designers might be interested in exploring trade-offs between the optimal solution and solutions in its vicinity. In order to provide an overview concerning the solutions in the proximity of the solution supplied by the optimization tool, a map of those so-lutions for the very first example in Table 5.13 is depicted in Figure 5.10 and Figure 5.11, where the number of turns and the inductor shape were fixed; varying the inductor track width, w, and the its inner diameter, din.

Figure 5.10: Inductance in the vicinity of the designed Inductor


121

From both figures (Figure 5.10 and Figure 5.11), and due to the high gradient that each map of solutions shows, it is possible to conclude that, for this case, if the quality factor is a figure of merit that ought to be taken into account, a designer may prefer to have less accuracy in the inductance value but, in other hand, to improve Q. From Figure 5.10 and Fig-ure 5.11, it is perceptible that an improvement around 20% in Q, with a deviation of 8% in the inductance is possible.

Figure 5.11: Quality factor in the vicinity of the designed Inductor

The results presented, even if in a few cases with errors around 10%, point out the po-tential of double π-model, combined with a MGA optimization procedure, when integrated in optimization design tools. This tool allows overcoming the typical limitation of the most non-commercial tools, regarding their limitation concerning the possibility for been integrated into an optimization loop.

5.3.3 Sensitivity Analysis

For the efficiency of the design process, analytical models are used to characterize cir-cuit elements. Although physics-based analytical expressions have been proposed for the evaluation of the lumped elements, the variability of the process parameters is usually ignored due to the difficulty to formalize it into an optimization performance index. The sensitivity of a circuit is the capacity to react with changes in certain parameters. It is considered as a meas-ure of how the circuit responds to an undesirable parameters variation.

Let H(s) be a transfer function of a ordinary circuit. The sensitivity is defined to be the relative variation of H(s) with respect to the variation of a circuit parameter, p, defined by

( )

( )( )p

sHsH

pSen sHp ∂

∂⋅=

(5.11)

Several works have been published in the recent years, regarding sensitivity analysis. As the number of elements in a circuit grows, analytical analysis is unfeasible either due to


122

the complex relation between parameters or device models. In this case, the strategy adopted in recent publications is a symbolic calculation method based on binary decision diagram or graph-pair decision diagram [95], [96] and [97].

The inductor simple π-model, due to its simplicity, allows an analytical characterization regarding circuit sensitivity, as well as an intuitive visualization of parameters correlation. In a more complex model, such as the double π-model, those parameters correspondence is not easily discerned. In Figure 5.12 is illustrated the relationship between three fabrication level parameters and the inductor Q and inductance, for the inductor simple π-model.

Figure 5.12: Process variables impact on inductor quality factor and inductance

According to [95], for a set of parameters dependent on a process variable, the circuit sensitivity can be computed by the following equation

( ) ( ) ik

kikk

ap

m

i

sHa

sHp SenSenSen ⋅= ∑

=1 (5.12)

In Figure 5.12 the inductor Q is dependent on Cox, which is dependent on oxide Thick-ness, tox. Taken into account (5.11), the quality factor sensitivity with respect to oxide thick-ness, is given by

ox

oxoxox

Ct

QC

Qt SenSenSen ⋅=

(5.13)

Moreover, the quality factor sensitivity concerning both oxide thickness and metal thickness, according to (5.12) can be obtained by

S

oxS

ox

oxoxtoxtox

Rt

QR

Ct

QC

QM

Qt

QMt SenSenSenSenSenSenSen ⋅+⋅=+=,

(5.14)

Quality Factor - Q

Inductance L

Oxide Thickness

Cox Csi

Metal Width

Metal Thickness

Rsi

Ls Rs

Length Davg Cs

Fabrication Level


123

5.3.3.1 Sensitivity Analysis Applied to Inductor Design

The complexity of the design as well as the necessity for having an environment offer-ing the possibility of exploring design trade-offs has led to the development of design method-ologies based multi-objective optimization procedures yielding the generation of Pareto-optimal surfaces. In this subsection the sensitivity analysis applied to a set of solutions, belonging to the design pareto front, will be performed. The robustness of each solution is evaluated, which allows designers to check its strength to parameters variation.

The design concerns the evaluation of four independent parameters, namely the track width (w), the number of turns (n), inductor shape (Nside), and the internal diameter (din). In this subsection the design of a 5 nH inductor for an operating frequency of 0.7 or 1.0 GHz for UMC130 technology is addressed, where the technological and physical parameters are shown in Table 5.3 and Table 5.4. The determination of the layout parameters is done ac-cording the optimization methodology before presented in Figure 5.8, where a maximum toler-ance in the inductance value, δ, of 5%, is imposed. The inductor design may be seen as a multi-objective problem; however, for the simplicity of the optimization algorithm, some of the objective functions were included as a series of constraints. In this example the inductor lay-out parameters yielding the maximum quality factor are generated. A maximum output diame-ter of 600 µm is considered, as well as the tolerance, δ, of 5% is guaranteed. The optimiza-tions results for the design of a 5 nH inductor, for operating frequencies of 0.7 and 1.0 GHz, are shown in Table 5.15 and Table 5.16, in that order.

Table 5.15: Optimization results for an inductor of 5 nH @ 0.7 GHz

w (µm) din (µm) Nturns Nside dout (µm) L (nH) Q Sens(Q(tox,t))

20.0 126.0 4.5 8 324 5.12 11.26 0.82

23.0 122.5 4.5 8 347 5.11 12.03 0.80

23.5 122.0 4.5 8 351 5.11 12.15 0.79

24.0 121.5 4.5 8 355 5.12 12.27 0.79

39.5 199.0 3.5 8 488 5.02 15.44 0.73

Table 5.16: Optimization results for an inductor of 5 nH @ 1.0 GHz

w (µm) din (µm) Nturns Nside dout (µm) L (nH) Q Sens(Q(tox,t))

20.0 123.0 4.5 8 321 5.11 14.55 0.74

23.5 117.5 4.5 8 347 5.09 15.37 0.72

33.5 190.5 3.5 8 438 4.88 17.69 0.66

37.0 187.0 3.5 8 459 4.9 17.92 0.64

37.5 188.5 3.5 8 464 4.95 17.92 0.63


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Regarding the results in Table 5.15 and Table 5.16, it is also possible to conclude that there is a commitment between Q and dout, i.e., when maximizing Q, the largest area is cho-sen. All the solutions present the same number of turns and geometric configuration. Regard-ing to the circuit sensitivity analysis, Sens(Q(tox,t)), the sensitivity drops as the quality factor increases. This fact is explained by the fact that as large the metal track width becomes, the metal resistance stays less dependent on metal thickness. On the other hand, as can be seen in Table 5.17, the Q can be considered tox independent. As stated, the solution with the high-est Q, is also the one that presents the lowest sensitivity. A sensitivity of 0.73, means that a change of 1% in the inductor parameters corresponds to a variation of 0.73% in the quality factor. In Table 5.17, the sensitivity of the quality factor to the variability of each of the pa-rameters analysed, is presented. Here it is possible to confirm that the quality factor presents almost total immunity to tox variability. The Q sensibility to tox is 0.012, in the case of a 5 nH inductor (0.7 GHz), which can be ignored. Although, and for the same inductor, the Q sensi-tivity regarding the metal thickness is 0.714.

Table 5.17: Sensitivity to variations in oxide (tox) and metal thickness (t)

Process variation 5 nH @ 0.7 GHz 5 nH @ 1.0 GHz Oxide

thickness Metal

thickness Sens Q(tox)

Sens Q(Mt)

Qmin Qmax Sens Q(tox)

Sens Q(Mt)

Qmin Qmax

± 10 % 0 %

0.012 0.714

15.42 15.46

0.013 0.617

17.89 17.94

0 % ± 10 % 14.33 16.51 16.82 19.00

± 10 % ± 10 % 14.28 16.52 16.75 19.00

5.4 Varactor Optimization-based Design

In an LC-VCO, the tank circuit is of major importance since it is responsible for produc-ing the required oscillatory signal. Moreover, the varactor is the element which gives to the oscillator the capability of being tunable.

In the literature several varactor models have been proposed aiming its integration in the tank characterisation of RF LC-VCOs design tool. In [98] an analysis of the impact of the VCO signal swing in the varactor capacitance over time is presented. However, results of the analysis have not been used as feedback inputs to the design process. A varactor model, based on the transistor equivalent circuit supported in BSIM3v3 model, with the addition of an overlap capacitance, is proposed in [99]. As a drawback, this model has to be supported either by adjustments inside the SPICE model in the optimization design loop, or adding a negative power supply to the model as a way to guarantee results accuracy. A physically based MOS varactor model, where charge modelling, physical geometry and parasitics are taking into account, is offered in [100] and [101]. Although, the set of equations needed to


125

evaluate the varactor capacitance are based in differential/integration techniques, which slows down the computation time, when included in a design optimization procedure. More recently, the design of a varactor by the means of evolutionary algorithms was proposed in [102] and [103]. However, this process is a time consuming task, taking several hours, since it relies on an exhaustive enumeration of designs where each combination of design parameters is validated through simulation.

This section aims to emphasize the skill of the proposed design tool, gathering the varactor model presented in section 3.3.1, and a genetic algorithm optimization procedure, as the path to reach optimal design of a varactor. For that purpose, the I-MOS varactor in back-to-back configuration, Figure 5.13, is chosen as the device to be optimized. The efficiency of the design procedure, as well as the accuracy of the results, is guaranteed by the use of a scalable varactor analytical model.

Figure 5.13: NMOS inversion-mode varactor

The optimization-based design flow for the proposed methodology is represented in Fig-ure 5.14. The design process starts with the creation of the population related to the variables that are going to be optimized, which can be discrete or continuous. The following step makes use of the EKV MOS transistor model parameters, previously obtained, in order to evaluate the varactor characteristics. Each combination of individuals is classified into a ranking, and a set of the best combinations are chosen for reproduction and mutation. This step is performed in loop until the optimization algorithm conditions are satisfied. Finally, the optimization proce-dure will test if specifications, as well as circuit feasibility are met.

Depending on the application some characteristics may be used for evaluating the qual-ity of the varactor design, such as the quality factor (Q) or the tuning range (CTR). These characteristics are influenced by varactor geometrical parameters as well as the technological parameters and constraints (if any). For the evaluation of the quality factor was considered

RCfπ(res.)cicleperenergydissipated(cap.)cicleperenergystoredQ

21

≈=

(5.15)

where the capacitance (C), is obtained through the set of equations offered in section 3.3.1 and

LW

NRR

fsquarepoly ⋅⋅= 2/

1

(5.16)


126

Create Initial PopulationW ∈ [Wmin, Wmax]L ∈ [Lmin, Lmax]

Nf ∈ [Nf min:stepNf :Nf max]

EKV ModelParameters

Evaluate Cost Function(Mapping Integer to Real Values)

Optimal or good solutions found?Select the best for Reproduction

Perform Mutation

Keep in loop until the optimization conditions are not satisfied

Feasible solutions?Specifications met?

Varactor Design Concluded

Varactor Design NOT possible

Varactor Design Specifications(Tech. Param., Frequency, Cap.)

YES

NO

Figure 5.14: Varactor optimization-based design flowchart

The tuning range is deemed as the variation range around the average capacitance in a oscil-lation period, and obtained by

minmax

minmax

CCCCCTR +

−±=

(5.17)

The optimization design tool was implemented with the Matlab GA toolbox. Since this toolbox shows several limitations for discrete optimization problems, where each variable has an imposed step-size, additional functions that deal with discrete variables were added (see 5.3.1.2). If a generic cost function is defined as Cost(W, L, Nf), as the cost function of the varactor design, the optimization problem can be symbolically represented by (5.18), with W as the transistor width, L the transistor length and Nf the number of fingers

( ) ( )( ) ( ) ( ) ectedfected

fTRf

CNLWCCtoSubject

NLWCorNLWQMaximize

expexp 1,,1

,,,,

⋅+≤≤⋅− δδ

(5.18)

Additionally, and regarding the optimization constraints, limits to the number of fingers were imposed. The finger length is fixed, as well as the space between two consecutive fin-


127

gers, to two times de minimal length. Finally, the maximum number of fingers is limited by the transistor width (and maximized by the user Table 5.18), as shown in (5.19).

min

minmax

24LN

LWN

f

f

⋅=⋅

=

(5.19)

Table 5.18: Varactor technological-physical parameters and optimization constraints

Parameters Value

Supply voltage (Vdd) 1.2 V

Tuning voltage (Vtune) 0.4 V

Rpoly/square 7.60 Ohm/square

Minimum Length (Lmin) 0.39 µm

Transistor Width (W) Wmin = 2·Lmin and Wmax = 300 µm

Transistor Length (L) Lmin = Lmin and Lmax = 4·Lmin

Number of fingers (Nf) Nf min = 1 and Nf max = 40

5.4.1 Varactor Design

In this subsection the design of a varactor aiming its integration in a LC tank circuit, with an inductor of 7 nH, will be addressed. Two examples considering the LC tank working at central operating frequencies of 1.0 and 2.5 GHz, for UMC130 technology are considered. The validity of the solution obtained is checked against results from simulation with HSPICE simulator. The design concerns the evaluation of three independent parameters, namely the transistor width (W), the transistor length (L) and the number of gate fingers (Nf). The GA optimization algorithm will deal with both continuous and discrete variables. The transistor width and length are considered as continuous variables, but the number of gate’s fingers is an integer value. Technological and physical parameters, as well as optimization constraints, are those shown in Table 5.18. For each of the two mentioned cases, two different objective functions are addressed. In example A, the varactor layout parameters maximizing the quality factor, Q, are computed; example B deals with designing a varactor with maximum tuning range. In both cases, to determine the required varactor capacitance, (5.20) is used. The capacitance tolerance (δ), is an additional constraint, with maximum value of 2.5%. The re-sults obtained are presented in Table 5.19, are compared with those obtained with HSPICE simulator. For the varactor design solution obtained when maximizing the quality factor, the corresponding capacitance over all range of the gate voltage is depicted in Figure 5.15.

LCπfosc 2

1=

(5.20)


128

The results presented in Table 5.19, highlight the capacity of the proposed design methodology to achieve optimal design of varactors. It is our conviction, that the results ob-tained are quite acceptable for an optimization methodology, without the needs of regular use of simulators during the optimization process, aiming its integration in a full LC-VCO optimiza-tion design procedure.

Table 5.19: Optimization results and its comparison with HSPICE simulations

Design

Parameters

Capacitance @ 1.0 GHz 3.62 pF

Capacitance @ 2.5 GHz 0.58 pF

A B A B W (µm) 233.68 299.53 64.64 133.93

L (µm) 1.44 1.14 0.84 0.44 Nf 39 26 38 10

Cav_model (pF) 1.78 1.76 0.283 0.294

Cav_HSPICE (pF) 1.67 1.70 0.274 0.312 Error (%) 7.13 3.51 2.90 5.86

Q 110.0 30.0 556.0 9.5

CTR (%) 92.71 93.22 94.31 98.26

Figure 5.15: Capacitance behaviour for the designed varactor

5.5 Conclusions

This chapter was dedicated to the optimization of both the integrated spiral inductor and the varactor. The design of the inductor and the varactor, is supported by a genetic algorithm optimization methodology, which is able to deal with continuous and/or discrete variables, making possible to satisfy both technological and layout constraints. The optimization proce-dure presented has three main advantages: i) as the inductor and varactor models are based in technological parameters, it may be straightforwardly adapted to new technologies; ii) re-


129

duced computation time, if compared with electromagnetic simulators; and iii) it can be easily integrated into an full LC-VCO optimization based design, as will be shown in the following chapter.

131

6 LC-VCO Design

The highlights on this chapter go to the full design of an LC-VCO. Firstly, the chosen topology is presented, and then the set of equations needed to characterize the oscillator be-haviour, are offered. Afterwards, different optimization strategies are proposed, and their ad-vantages and/or disadvantages are described. Then, the LC-VCO adopted design optimiza-tion methodology, taking into account the circuit topological and physical constraints, is de-tailed. Finally, a set of working examples are offered.

6.1 Introduction

The demand for low-voltage and low-power design has resulted in circuits operating at the limits of the required performance. In general, analog circuit designs, such as the design of an LC-VCO, are aimed at fulfilling a set of specifications resulting from specific application working conditions.

When dealing with high frequency applications, LC-VCO topologies are preferred to other structures, such as relaxation or ring oscillators [104]. Among several different LC oscil-lators structures, the CMOS cross-coupled LC-VCO presents better noise performance and better rise and fall time symmetry [105], where the two most implemented topologies are the single-switch VCO and the double switch VCO, depicted in Figure 6.1. Both LC-VCO topolo-gies share the concept of providing a negative resistance in order to compensate the losses that come from the resonator. With this technique it is possible to achieve high oscillation am-plitude, thus increasing the phase noise performance. The control over the negative resistance is usually done by means of a tail current source, represented by transistor Mb in Figure 6.1. The introduction of the current source, however, will reduce the output voltage swing available for oscillation [50].

LC-VCO Design

132

a) Single-switch VCO b) Double-switch VCO

Figure 6.1: Circuit schematic of an LC-VCO

Regarding the two LC-VCO topologies presented in Figure 6.1, the main differences be-tween stem from: the placement of the resonator and in the oscillation frequency. In the sin-gle-switch structure two integrated inductors are used, then occupying larger area. In the case of a double-switch VCO, due to the presence of the PMOS pair, a single inductor may be used. Yet, in the double-switch topology the parasitic capacitances Cgs and Cgd that appears due to the PMOS cell, will affect both the tuning range and the oscillation frequency. From the small signal analysis, it is well known that the double-switch VCO shows an output signal amplitude that is the double when compared to the one achieved with the single-switch topol-ogy, if the same current consumption is considered. Additionally, lower phase noise is reached for higher oscillation amplitude. The weakness of the double-switch VCO is the need of higher voltage supply when compared to the single-switch VCO, due to the use of the PMOS stage.

When designing an oscillator, the aspect to which most designers care about is the trade-off between power consumption and phase noise. Thus, in this work the double-switch topology will be considered as the test case for the proposed optimization design methodol-ogy.

In the following section, the LC-VCO circuit characterization is presented. Afterwards, the different optimization strategies that can be applied to the design of a full oscillator are offered. Results achieved with the proposed design methodology followed by a discussion re-garding the achievements made are then presented.

LC-VCO Design

133

6.2 LC-VCO Characterization

The model based LC-VCO design relies on the oscillator analytical characterization. A double-switch VCO with a current source is illustrated in Figure 6.2. As mentioned before, the oscillator has as main block the tank resonator formed by the inductor (L) and two tunable capacitors (Cvar). The double cross-coupled PMOS (MP) and NMOS (MN) transistors compen-sate the tank losses by providing a negative resistance, and finally the current source that allows to control the overall power consumption.

Figure 6.2: Double-switch LC-VCO with a current source

Concerning the full LC-VCO characterization, the fundamental equations as well as some others constrains inherent to the circuit behaviour, are as following:

• The oscillation frequency, assuming an non ideal inductor and an ideal varactor ( CL // ) and start-up oscillation condition are given by

LCR

LCπfosc

2

12

1−⋅= (considering

CL

LCjXjXR

Y−

++

=11

)

(6.1)

activemaxtank, gg ≤⋅α

(6.2)

where α is the starter factor - which is at least one, and in practise is usually set in the range of 2-3 in order to assure the start-up condition; gtank and gactive are the tank and active con-ductances, respectively. The resistance R in (6.1) models the tank losses. The tank quality factor (Q) is estimated by

var

111

CLTank QQQ+=

(6.3)

LC-VCO Design

134

It can be shown that the tank quality factor is obtained by

LRQ P

Tank ω=

(6.4)

where RP is the equivalent tank resistance (parallel association of the inductor and the varac-tor resistances), ω the oscillation frequency and L the inductor inductance. Often the capacitor has higher quality factor than inductors in silicon integrated processes, which means that (6.3) can be written

LTank QQ ≈ (6.5)

and the equivalent RP resistance may be obtained with

LLLL

PL

P RQRR

LRR

LL

R⋅=⋅

=⇒≈ 2

2ωω

ω (6.6)

In general, the negative resistance provided by the cross-coupled transistor pairs must over-come all real resistive losses in the oscillator circuit. Ideally, an oscillator has no losses with infinite voltage swing at precisely one frequency, so (6.1) can be reformulated as

LCπfosc 2

1=

(6.7)

and to guarantee that oscillation occurs, the total transconductance (gm) of the active devices must verify the condition

LRCgm ≥

(6.8)

The LC-VCO performance is affected by the parasitics associated to each element, repre-sented in Figure 6.3, where MOS transistors and the current source are considered as ideal devices. Due to the circuit symmetry and assuming that no a.c. voltage appears between each element, the dashed line can be considered as a virtual ground. Therefore the total capaci-tance that appears at the output node is

LoadNMOSPMOS CCCCC +++= vartotal

(6.9)

thus the oscillation frequency is

( ) totalosc CLπ

f⋅

=221

(6.10)

Regarding the start-up oscillation condition, the total circuit conductance is given by

nds,pds,varL

tank 22ggggg +++=

(6.11)

LC-VCO Design

135

CVAR CVAR

L/2L/2

RP/2 RP/2

CLOAD CLOAD

gm,N gm,N

gds,N gds,N

CNMOS CNMOS

CPMOS CPMOS

gm,P gm,P

gds,P gds,P

IBIAS

Vdd

IdealIdeal

IdealIdeal

PMOSCross-coupled

pair

LC Tank

NMOSCross-coupled

pair

Figure 6.3: Double-switch LC-VCO with parasitic elements

where the inductor and varactor conductance are respectively [106]

( )2L 2 LfRgosc

L

π= and ( ) var

2maxvar,var 2 RCfg osc ⋅= π

(6.12)

with RL and Rvar the inductor and varactor resistances. The transistor drain-to-source conduc-tance, which are based on the EKV transistor model, are obtained by [23]

rT

rsRs iU

iIIg+⋅⋅

⋅≈=

25.05.0d λ (6.13)

where λ is the channel length modulation. The circuit transconductance is estimated by

gs

ds

VIg

∂∂

=m

(6.14)

LC-VCO Design

136

and the active transconductance of the circuit is given by

nm,pm,active ggg +=

(6.15)

• The differential output voltage, 2·Vtank, is determined as in

tank

biastank

I4Vgπ

=

(6.16)

In order to supply enough voltage swing to the following circuit, Vtank can be limited to Vtank,min. The oscillation tuning range is given by

min total,max total, CL1ω

CL1

≤≤

(6.17)

where the VCO capacitance, is dependent on the varactor capacitance.

• If the circuit power consumption is an limitation, the following constraint can be im-posed,

maxIIbias ≤

(6.18)

• Phase-noise is an elementary characteristic of a VCO that depicts the purity of the os-cillation signal in the vicinity of the oscillation frequency fosc. In this work, the VCO phase-noise is obtained through [75]

( ) ( )[ ]

+++⋅⋅

∆=∆ nd0,pd0,varLB2

tank

42tank

22 2V2L

161log10 ggggTKfL osc

ff γ

ππ

(6.19)

where KB is the Boltzman constant, T the absolute temperature in Kelvin, gd0 is the drain conductance when VDS=0, and γ is the excess noise factor. The drain conductance is calcu-lated by

satchannel

bias

ELIg

⋅=0d

(6.20)

with Lchannel meaning the transistor channel length and Esat the electric field saturation.

• The design of an oscillator may involve several design criteria that could turn up from specifications, technology or even from parameters constraints, thus, somehow, their perform-ance should be possible of being compared to other oscillators. The usual metric to assess the oscillator performance is the so called Figure of Merit (FoM). The FoM is a valuable and fair way to compare oscillators’ performance, since it is independent of the technology used, allowing designers to measure where their design is positioned in relation to other oscillators. The most commonly used FoM in the RF community is [105]

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(6.21)

where Pdc is the DC power dissipated. This FoM deals with most difficult challenges in an os-cillator design, which is to reach simultaneously a low phase noise and minimum power con-sumption.

6.3 LC-VCO Optimization Strategy

The design flow for the proposed optimization based LC-VCO design is represented in Figure 6.4. The automated design consists of:

• Technology Selection: a set of parameters that represent physical and electrical proper-ties of the used technology, such as metal, oxide and substrate thickness, metal and sheet resistance, oxide and substrate permittivity, ...

• Specifications Input: a set of typical values like the desired oscillation frequency, mini-mum phase noise at a given offset frequency and maximum power consumption.

• Design Optimization Start-up: in this step are uploaded all the parameters related with the technology chosen, as well as the MOS EKV parameters that allow to characterize the transistors behaviour. If the EKV parameters are not available, the tool invokes a subroutine that proceeds with the EKV parameters extraction.

Figure 6.4: Flowchart of the LC-VCO design tool

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• Optimization Loop: at this point the optimization of the oscillator design is done. It re-turns a sized LC-VCO circuit, if feasible solutions are found.

The optimization design flowchart is detailed in Figure 6.5. Considering the LC-VCO to-pology illustrated in Figure 6.2, the design process goes through a parallel optimization; this means that all the elements sizes (cross-coupled transistors, varactors and the inductor) are optimized at the same time. This parallel optimization strategy has a larger search space and can achieve a better compromise among all the variables being optimized, in opposition to a sequential optimization. In a sequential optimization, each block (inductor, varactor and active elements) is optimized individually, and the result of each block influences the following one. The advantage of this method is that the optimization algorithm deals with a small number of variables at each time, and may run faster. Although, in this work, the abovementioned paral-lel optimization is adopted at the cost of some computation time.

Figure 6.5: LC-VCO optimization design flowchart

The optimization process, based on genetic algorithms, starts with an initial population of candidates that comprises all the variables being optimized regarding all the elements sizes. In this way, the same attention is simultaneous put on several design issues such as the phase noise - since the drain current in each transistor is the dominant contributor to the phase noise, the minimization of the losses – mainly due to the inductor, and the oscillation frequency – imposed by the tank circuit. After the first round if feasible solutions from the

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physical (layout) point of view are found, specifications and constraints are verified. The opti-mization process continuous by generating a new population of candidates, aiming to find the best solution, or a set of the best solutions, that accomplish both the specifications and the optimization cost function; restricted to topological and physical constraints. The overall optimi-zation procedure main goal will consist on the minimization of both the circuit power consump-tion and phase noise, be means of the LC-VCO figure of merit (FoM).

6.3.1 LC-VCO Design: Optimization Approach

It is well accepted that the complexity of LC-VCO circuit design is correlated to the number of variables involved. Moreover, the time needed by the optimization algorithm to achieve a final design solution is also dependent of the number of variables being optimized. Thus, different optimization approaches can be followed depending on which element(s) must go through the optimization process, as illustrated in Figure 6.6. Three different scenarios are depicted in Figure 6.6, where the green boxes represent elements to be optimized, the orange boxes identify elements that are to be optimized but in have initial constraints imposed by the designer, and finally the red boxes represented elements that somehow are fixed. Each of these three scenarios a detailed explanation of each of these three scenarios is now given:

• Simple Approach: In this situation just the LC tank circuit goes through the optimization process. The output DC voltage (Vout), the voltage at the current source node (Vx), the current Ibias, and length of all the transistors are fixed by the designer. Therefore all the active elements sizes can be straightforwardly determined. Only the LC resonator needs to be optimized. The number of variables is minimum, and the full circuit design can be reached in seconds or in a few minutes.

• Moderate Approach: In this scenario, besides the resonator the optimization algo-rithm deals with the design of the cross-coupled transistor pairs as well as the current source transistor (Mb). Although, some parameters can be fixed, such as the transistor length or the output DC voltage (Vout).

• Hard Approach: This is the most time consuming approach, since it deals with the maximum number of variables being optimized. There is not initial fixed characteristic, so the optimization procedure need to deal with a high level of correlation between some of the circuit parameters, such as is the case of the DC output voltage and cur-rent, power consumption is dependent on current, the output voltage is at the same time the gate voltage of the cross-coupled pair transistors which influences the transis-tor conductance and transconductance and consequently the phase noise.

A qualitative comparison of the three mentioned scenarios either for parallel and se-quential optimization approach is depicted in Figure 6.6d.

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a) Simple Approach

b) Moderate Approach

c) Hard Approach

d) Time vs Number of variables graph

Figure 6.6: LC-VCO design: Optimization Approach

6.4 Results and Discussion

In this section the layout (elements size) of a full LC-VCO obtained with the proposed methodology is presented. The oscillator optimization design was implemented in Matlab and uses the Genetic Algorithms (GA) toolbox. The design of LC-VCOs for different operating fre-quencies, in the range of a few GHz, in UMC130 technology is addressed. Due to the differ-ent design specificity, namely in what concerns the continuous/discrete nature of the design variables, the proposed design methodology approach deals with four major optimization proc-esses: the inductor optimization, the varactor optimization, the active elements, and the LC-VCO performance optimization, regarding phase noise and power consumption.

For the planar inductor design, the methodology adopted aims to achieve a technol-ogy/topology-aware solution. Also to be accounted for is the discrete nature of the design

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variables, as well as, the correlation between them. The design concerns the evaluation of four independent parameters, namely the track width (w), the number of turns (n), inductor shape (Nside), and the internal diameter (din). The design of the varactor concerns the evalua-tion of three independent parameters, namely the transistor width (Wvar), the transistor length (Lvar) and the number of gate fingers (Nf). The GA optimization algorithm deals with both con-tinuous and discrete variables. The varactor (transistor) width and length are considered as continuous variables, but the number of gate’s fingers is an integer value. At last, the design of the cross-coupled pairs as well as the current source transistor engage the optimization of six correlated parameters; the PMOS transistors (Mp) width (Wp) and length (Lp), the NMOS transistors (Mn) width (Wn) and length (Ln), the bias transistor (Mb) width (Wb) and length (Lb). The LC-VCO design is supported by an equation-based optimization strategy. Thus, the technological and physical parameters regarding the technology used must be known. Such parameters are given in Table 6.1.

Table 6.1: Inductor and transistor technological-physical parameters

Parameters Value

Indu

ctor

Metal thickness (t) 2.8 µm

Sheet resistance (Rsheet) 10 mΩ/ square

Oxide thickness (toxide) 5.42 µm

Oxide permitivity (εoxide) 4ε0

Substrate thickness (tsubrate) 700 µm

Substrate permitivity (εsubrate) 11ε0

Substrate resistivity (ρsubrate) 28 Ω-cm

Tran

sistor

NMOS tox 2.73 nm

PMOS tox 2.86 nm

Rpoly/square 7.60 Ohm/square

Early voltage 9.5e4 V

Temperature 300.15 K

Regarding the LC-VCO performance, the optimization objective functions are the mini-mization of both the phase noise and the power consumption by means of the figure of merit (FoM) (6.21). The VCO envisaged characteristics and design constraints are given in Table 6.2. Furthermore, the devices parameters range adopted in this work are offered in Table 6.3, where the minimum transistor length is assumed as three times the minimal length allowed by the technology. The results obtained with the proposed methodology will be checked against those obtained through HSPICE (BSIM3v3)/RF simulations.

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Table 6.2: LC-VCO design constraints

Parameters Value

Max. inductor outer diameter (Dout) 600 µm

Inductance (L) 0.5 – 15 nH

Tank capacitance (Cvar) 0.5 - 20 pF

Bias current (Ibias) 0.2 – 3.0 mA

Output DC voltage (Vout) 0.35 – 1.00 V

Output voltage swing (Vtank) VDD/8 - VDD/2

Max. desviation to the desired Fosc 5 %

Load capacitance (CLoad) 0.1 pF

Table 6.3: Design parameters range

Parameter Min Step Max

Indu

ctor

w (µm) 5.0 0.25 50.0

din (µm) 20.0 0.25 250.0

n 1.5 1.0 15.5

Nside Square (4) / Hexagonal (6) / Octagonal (8)

Tran

sisto

r W (µm) 2·Lmin -- 500.0

L (µm) 0.8·Lmin -- 1.2·Lmin

Nf (varactor) 1.0 1.0 16.0

The following sections are dedicated to present the LC-VCO design results. As previ-ously mentioned, when designing an oscillator, designers can go from a simple to a hard de-sign approach. In this work, three cases will be considered.

6.4.1 LC-VCO Simple Approach Optimization

As the full optimization of an LC-VCO engages approximately a dozen variables, a re-duction on this number of variables can be attained by imposing the bias current. The idea of the simple approach optimization is to reduce the oscillator design to the design of the reso-nator. Thus, the design tool will consider the optimization of seven independent parameters: four regarding the inductor, plus three concerning the varactor. For the inductor design the track width (w), the number of turns (n), the inductor shape (Nside), and the internal diameter (din) are considered. The varactor optimization comprises the transistor width (W), length (L) and number of gate fingers (Nf).

For the optimization process, carried out by genetic algorithms, a population size of 100 individuals is adopted. Additionally, the maximum population generations are limited to 250,

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and if the best solution remains the same for 25 generations, the algorithm stops. In this sec-tion the design of a LC-VCO for operating frequencies of 1.0, 1.5, 2.0, 2.4 and 2.8 GHz are addressed. The oscillator characteristics that are assumed of being fixed during the optimiza-tion process are given in Table 6.4.

Table 6.4: LC-VCO design characteristics (Simple Approach)

Parameters Value

Center frequency - Fosc & ∆f 1.0, 1.5, 2.0, 2.4, 2.8 GHz / 1 MHz

Vdd 1.2 V

Output DC voltage (Vout) 0.8 V

DC voltage at bias node (Vx) 0.4 V

Bias current (Ibias) 1.0 mA

Varactor control voltage (VControl) 0.4 V

Current source gate voltage (VG(Mb)) 0.4 V

In this optimization scenario, the active elements sizes are imposed by the bias current and by the DC voltage at each node of the circuit. Consequently, the transistors sizes are independent of the optimization process, therefore, independent of the oscillation frequency. For all the following optimization examples, the LC-VCO transistors dimensions are presented in Table 6.5.

Table 6.5: LC-VCO transistors sizes

Parameters Wp (µm) Lp (µm) Wn (µm) Ln (µm) Wb (µm) Lb (µm)

Value 217.9 0.39 76,7 0.39 71.2 0.39

6.4.1.1 LC-VCO Design - 1.0 GHz

For this first oscillator design, aiming for an oscillation frequency of 1.0 GHz, the design regarding the size of the resonator elements is offered in Table 6.6. The LC-VCO characteris-tics obtained through the proposed methodology as well as those obtained through HSPICE (BSIM3v3) and HSPICE RF simulations are offered in Table 6.7. The need of estimating the simulated circuit phase noise, requires the use of HSPICE RF. For the d.c. and a.c. analysis the HSPICE was used.

Table 6.6: Resonator elements size (1.0 GHz)

Inductor ( L=13.4 nH, Q=9.2) Varactor (Cvar=1.47 pF )

w (µm) din (µm) N turns Shape W (µm) L (µm) Nf

10.00 56.75 8.5 4 452.8 0.46 16

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Table 6.7: Optimization design results vs simulation (1.0 GHz)

Parameters fosc

(GHz)

L1MHz

(dBc/Hz)

Ibias (mA)

Pdc

(mW)

FoM (dBc/Hz)

Voutamp

(V)

Optim. 1.00 -123.2 1.00 1.20 182.5 0.39

Simulation 1.01 -126.9 0.95 1.13 186.5 0.45

Error (%) 0.9 2.9 5.3 6.2 2.1 13.3

In Figure 6.7 the VCO output signals for an oscillation frequency of 1.0 GHz are pre-sented. The VCO phase noise characteristic is also illustrated in Figure 6.7. The output signal oscillates between 0.28 and 1.18 V, which represents a tank output swing of 0.9 V. Also, at the centre frequency (1.0 GHz), the oscillator phase noise reaches to -126.9 dBc/Hz, in the vicinity of 1 MHz.

Figure 6.7: LC-VCO output signal (Vout1 and Vout2) @ 1.0 GHz

In all the VCO characteristics shown in Table 6.7, the error is always less than 10% (except for the output voltage swing), showing a quite good agreement between predicted and simulations results. The results obtained by simulation are better in all parameters than those attained with the optimization tool, which improves the performance of the final circuit if com-pared to the expected one. Moreover, the use of a tunable capacitor provides the VCO with the possibility of reducing this error. Regarding the oscillator tuning range, during the optimiza-tion design the varactor control voltage was fixed to 0.4 V, as this is the value for which the varactor shows a wider tuning range (see, Figure 3.15). Thus, and assuming that the control voltage varies between 0.2 and 0.8 V, the estimated tuning range is about 20%. Through

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simulation the oscillation frequency for a control voltage of 0.2V was 0.93 GHz, and for 0.8 V was 1.17 GHz, which performs a tunable range of 24%.

For the design of the LC-VCO circuit, the proposed tool took 15 seconds to compute and evaluate 27 populations of 100 individuals each, which had resulted in 395 feasible solu-tions for the design of the oscillator.

To access to the evolution of the optimization algorithm during the design process, the results obtain in each generation expressed by means of boxplots (or whisker diagram), illus-trating the spread of a set of data, and thus indicating the convergence of the optimization results. In Figure 6.8 a boxplot for the phase noise is presented.

Figure 6.8: Phase noise evolution through each generation

The boxes represent the range of values of 50 per cent of the total data, called the in-ter-quartile range, where the line inside the box is the median value. The upper quartile represents the highest 25 per cent of the data, and is represented in the whisker above the box. Finally, the lowest 25 per cent of the data, the lower quartile, is shown under the box limits. From Figure 6.8 it is possible to observe that just on the fifth population generation a first feasible solution(s) for implementing the LC-VCO was found by the algorithm. As the first column of the boxplot is represented by a single line, all the solutions found has the same value. As new populations are generated, a range of new practicable solutions are found, as can be seen between the fifteenth and the twentieth generations. Then, the algorithm starts to converge for a final and best solution – in accordance to the cost function evaluation – and in the last population all the solutions converged to the same phase noise value.

In Figure 6.9 a boxplot showing the evaluation of the oscillation frequency for all the feasible solutions found, is depicted. The frequency distribution over all the generations follows

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a similar behaviour as in the case of the phase noise. Although, a larger variation in the fre-quency is verified between the fifteenth and the twentieth generations, after that point, the so-lutions converge to a final value. A maximum deviation of 5% for any feasible solution, im-posed by the optimization constraints, is also verified in this boxplot.

Figure 6.9: Oscillation frequency evolution through each generation


At this point, the design of a LC-VCO for an operation frequency of 1.5 GHz was per-formed, and the resonator elements size is depicted in Table 6.8. Additionally, the results ob-tained with the proposed methodology as well as those obtained through HSPICE (BSIM3v3) and HSPICE RF simulations are offered in Table 6.9.




8.00 72.00 6.5 4 336.8 0.46 15


Parameters fosc

(GHz) L1MHz (dBc/Hz)

Ibias (mA)

Pdc (mW)

FoM (dBc/Hz)

Voutamp (V)

Optim. 1.47 -118.4 1.00 1.20 181.0 0.39

Simulation 1.42 -123.6 0.95 1.13 186.1 0.40

Error (%) 3.5 4.2 5.3 6.2 2.7 2.5

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The VCO output signals for an oscillation frequency of 1.5 GHz and the phase noise characteristic are depicted in Figure 6.10. As can be observed the output signal varies be-tween 0.39 and 1.18 V, which represents a tank output swing of 0.8 V. Moreover, at the cen-tre frequency of 1.5 GHz, the oscillator shows a phase noise of -123.6 dBc/Hz in the vicinity of 1 MHz.


The predict VCO characteristics obtained by the optimization are in line to those ob-tained by simulations, showing an error around 5%, as can be observed in Table 6.9. In what concerns the oscillator tuning range, as for the previous example, the varactor control voltage was fixed to 0.4 V. Thus, and assuming that the control voltage varies between 0.2 and 0.8 V, the estimated tuning range is about 17%. Through simulation the oscillation frequency for a control voltage of 0.2V was 1.33 GHz, and for 0.8 V was 1.67 GHz, which performs a tun-able range of 22%.

Regarding the design computation time, the algorithm ran for 15 seconds and performed the evaluation 27 populations of 100 individuals each, which yielded 594 feasible solutions for implementing the oscillator.


The design of a LC-VCO working at a frequency of 2.0 GHz was performed. The tank circuit elements’ sizes, achieved by the optimization design tool are offered in Table 6.10. The

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results obtained with the proposed methodology as well as those obtained through HSPICE (BSIM3v3) and HSPICE RF simulations are given in Table 6.11.




10.00 201.75 3.5 8 280.8 0.41 14


Parameters fosc

(GHz)

L1MHz

(dBc/Hz)

Ibias (mA)

Pdc

(mW)

FoM (dBc/Hz)

Voutamp

(V)

Optim. 1.94 -114.5 1.00 1.20 179.5 0.39

Simulation 1.80 -117.9 0.95 1.13 182.5 0.38

Error (%) 7.7 2.9 5.3 6.2 1.6 2.6

The VCO output signals for an oscillation frequency of 2.0 GHz and the phase noise characteristic are depicted in Figure 6.11. As can be observed the output signal varies be-tween 0.41 and 1.18 V, which represents a tank output swing of 0.77 V. The circuit shows a phase noise of -117.9 dBc/Hz in the vicinity of 1 MHz regarding the centre oscillation fre-quency.


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The data reported in Table 6.11 shows that the error between expected and simulated results is quite acceptable and situated in the neighbourhood of 5%. Although, the oscillation frequency obtained by simulating the designed circuit is 10% far from the desired one. This happens due to the difficulty of predicting the parasitics effects in the active elements at high frequencies. However, the simulated circuit shows a tuning range of 15% (fmin – fmax), for a control voltage in the range of 0.2 – 08 V, which allows the circuit to adjust its frequency to the required oscillations frequency. The simulated tuning range is in accordance with that es-timated by the design tool (15%).

Concerning the design computation time, the algorithm ran for 16 seconds and per-formed 2700 evaluations that have resulted in 594 solutions.


In this fourth working example, the design of a LC-VCO aiming a centre oscillation fre-quency of 2.4 GHz was performed, and the dimensions of the resonator elements are given in Table 6.12. The results obtained with the proposed methodology as well as those obtained through HSPICE (BSIM3v3) and HSPICE RF simulations are offered in Table 6.13.




10.75 235.25 2.5 6 257.8 0.46 16


Parameters fosc

(GHz) L1MHz (dBc/Hz)

Ibias (mA)

Pdc (mW)

FoM (dBc/Hz)

Voutamp (V)

Optim. 2.42 -113.3 1.00 1.20 180.2 0.37

Simulation 2.23 -117.0 0.95 1.14 183.4 0.35

Error (%) 8.5 3.1 5.3 5.2 1.7 5.7

The output waveforms of the designed VCO, as well as its phase noise characteristic are illustrated in Figure 6.12. In the proposed circuit, the output signal varies between 0.47 and 1.17 V, which represents a tank output swing of 0.7 V. The circuit shows a phase noise of -117.0 dBc/Hz in the vicinity of 1 MHz regarding the centre oscillation frequency.

The reported data in Table 6.13 reveals the accuracy between estimated and simulated results. The errors are quite reasonable and highlight the performance of the proposed tool. Regarding the oscillator tuning range, during the optimization design the varactor control volt-age was fixed to 0.4 V. Thus, and assuming that the control voltage varies between 0.2 and

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0.8 V, the estimated tuning range is about 15%. Through simulation the oscillation frequency for a control voltage of 0.2V was 2.12 GHz, and for 0.8 V was 2.47 GHz, which performs a tunable range of 16%.

The design tool during optimization process, has evaluated 2700 cost functions in 15 seconds.



The fifth working example comprises the design of a LC-VCO working at a frequency of 2.8 GHz. The resonator devices sizes are given in Table 6.14. The results obtained with the proposed methodology as well as those obtained through HSPICE (BSIM3v3) and HSPICE RF simulations are offered in Table 6.15.

The voltage signal at the output node and the VCO phase noise characteristic are illus-trated in Figure 6.13. In the proposed circuit, the output signal varies between 0.53 and 1.13 V, which represents a tank output swing of 0.6 V. The circuit shows a phase noise of -112.2 dBc/Hz in the vicinity of 1 MHz regarding the LC-VCO oscillation frequency.




16.75 229.5 2.5 8 247.8 0.36 16

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Parameters fosc

(GHz)

L1MHz

(dBc/Hz)

Ibias (mA)

Pdc

(mW)

FoM (dBc/Hz)

Voutamp

(V)

Optim. 2.74 -111.2 1.00 1.20 179.2 0.38

Simulation 2.48 -112.2 0.95 1.14 179.5 0.30

Error (%) 10.5 0.9 5.3 5.2 0.2 26.6


The results presented in Table 6.15 show a reasonable accuracy between expected and simulated results. The circuit oscillation frequency achieved by simulation is 11% far from the desired frequency. Although, for an equation based optimization, which aims to be a first ap-proach design, this result is quite satisfactory.

The simulated circuit shows a tuning range of 16% for a control voltage in the range of 0.2 – 08 V, which gives to the circuit the ability to adjust the oscillation frequency to a value very near to the required frequency. The simulated tuning range is in accordance with that estimated by the design tool (15%).

Regarding the design computation time, the algorithm ran for 11 seconds and evaluated 783 feasible solutions for implementing the LC-VCO.

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6.4.2 LC-VCO Moderate Approach Optimization

The moderate approach optimization is a small step ahead relatively to the previous situation – simple approach. Here, besides the resonator optimization the tool also deals with the optimization of the active elements. Although, and in order to reduce the design complex-ity, some relationships regarding the active elements sizes are imposed. Thus, the design tool will consider the optimization of eight independent parameters. Additionally to the previous seven parameters used in the simple approach optimization (four regarding the inductor, plus three concerning the varactor), the transistors width are here considered (Wn).

The introduction of a new design variable brought additional complexity to the optimiza-tion algorithm, since the output DC voltage (Vout) and the DC voltage at bias node (Vx), which are determined by the circuit current, are now dependent on the transistors sizes. Moreover, the current through the circuit directly influences some of the VCO characteristics, such as the output voltage amplitude and the transistors transconductance, which in the end changes the circuit phase noise and power consumption.

For the optimization process, carried out by genetic algorithms, a population size of 100 individuals is still adopted. Additionally, the maximum population generations are limited to 250, and if the best solution remains the same for 25 generations, the algorithm stops. In this section the design of a LC-VCO for operating frequencies of 1.0, 2.0 and 2.8 GHz are con-sidered. The oscillator characteristics that are assumed of being fixed, as well as the relation between transistor width and length sizes, during the optimization process are given in Table 6.16.

Table 6.16: LC-VCO design characteristics (Moderate Approach)

Parameters Value

Center frequency - Fosc & ∆f 1.0, 2.0, 2.8 GHz / 1 MHz

Vdd 1.2 V



Transistor length Lp = Lb = Ln= Lmin 0.39 µm

PMOS transistor width (Wp) 0.5·β0n/β0p·Wn

NMOS bias transistor width (Wb) 2·Wn


For this first oscillator design, aiming for an oscillation frequency of 1.0 GHz, the size of the VCO elements is offered in Table 6.17. The results obtained with the proposed methodol-

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ogy as well as those obtained through HSPICE (BSIM3v3) and HSPICE RF simulations are offered in Table 6.18.

Table 6.17: VCO elements size (1.0 GHz)

Active Elements Inductor ( L=13.0 nH, Q=10.1) Varactor (Cvar=1.53 pF )

Wp (µm)

Wn (µm)

Wb (µm)

w (µm)

din (µm)

N turns Shape W

(µm) L

(µm) Nf

186.4 67.8 135.6 22.50 182.5 5.5 8 471.8 0.46 13


Parameters fosc

(GHz)

L1MHz

(dBc/Hz)

Ibias (mA)

Pdc

(mW)

FoM (dBc/Hz)

Voutamp

(V)

Optim. 1.02 -120.7 1.90 2.27 177.2 0.48

Simulation 1.07 -127.1 1.76 2.11 184.4 0.59

Error (%) 4.7 5.0 7.9 7.6 3.9 18.6


In Figure 6.14 the VCO output signals of the designed circuit, for an oscillation fre-quency of 1.0 GHz, are presented. The VCO the phase noise characteristic is also illustrated in the same figure. The output signal oscillates between 0.0 and 1.2 V, which represents a full output swing of 1.2 V. Also, at the centre frequency (1.0 GHz), the oscillator phase noise reaches to -127.1 dBc/Hz, in the vicinity of 1 MHz. Regarding the DC voltage at nodes Vout

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and Vx,, by simulation the values obtained were: Vout = 0.74 V and Vx = 0.30 V. The values achieved by the design tool were 0.73 and 0.28 V respectively for Vout and Vx.

It is possible to observer from the data represented in Table 6.18 that the power con-sumption is relatively high for a low consumption device. The current range assumed as suit-able for the circuit design is 0.2-3.0 mA, and as the cost function in the optimization algo-rithm is the figure of merit (FoM), the algorithm will try to reduce both the phase noise and the power consumption. Although, in what concerns the circuit current, the phase noise de-creases by a power of two and, in the other hand, the power consumption is directly propor-tional to the current. Thus, as current raise the phase noise decreases more rapidly than power consumption decreases as current drops.

In all the VCO characteristics shown in Table 6.18, the error is always less than 10% (except for the output voltage swing), showing a quite good agreement between predicted and simulations results. Regarding the oscillator tuning range, during the optimization design the varactor control voltage was fixed to 0.4 V. Thus, and assuming that the control voltage var-ies between 0.2 and 0.8 V, the estimated tuning range is about 21%. Through simulation the oscillation frequency for a control voltage of 0.2V was 1.00 GHz, and for 0.8 V was 1.26 GHz, which performs a tunable range of 24%.

For the design of the LC-VCO circuit, the proposed tool took 224 seconds to compute and evaluate 27 populations of 100 individuals each, which has resulted in 577 feasible solu-tions for the design of the oscillator.


This second working example comprises the design of a LC-VCO working at a fre-quency of 2.0 GHz, where the LC-VCO devices’ sizes are given in Table 6.19. The results obtained with the proposed methodology as well as those obtained through HSPICE and HSPICE RF simulations are offered in Table 6.20.

The voltage signal at the output node and the VCO phase noise characteristic are illus-trated in Figure 6.15. In the proposed circuit, the output signal varies between 0.10 and 1.18 V, which represents a tank output swing of 1.08 V. The circuit shows a phase noise of -112.8 dBc/Hz in the vicinity of 1 MHz regarding the LC-VCO oscillation frequency.



Wp (µm)

Wn (µm)

Wb (µm)

w (µm) din

(µm) N turns Shape

W (µm)

L (µm)

Nf

123.1 44.8 89.6 13.25 219.25 3.5 8 310.8 0.41 15

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Parameters fosc

(GHz)

L1MHz

(dBc/Hz)

Ibias (mA)

Pdc

(mW)

FoM (dBc/Hz)

Voutamp

(V)

Optim. 1.90 -113.8 1.25 1.50 177.6 0.45

Simulation 1.95 -122.8 1.16 1.39 187.2 0.54

Error (%) 2.6 7.3 7.8 7.9 5.1 16.0


The results presented in Table 6.20 show a reasonable accuracy between expected and simulated results. The simulated circuit shows a tuning range of 18% for a control voltage in the range of 0.2 – 08 V, which gives to the circuit the ability to adjust the oscillation fre-quency to a value very near to the required frequency. The simulated tuning range is in ac-cordance with that estimated by the design tool (20%).

Regarding the design computation time, the algorithm ran for 145 seconds and evalu-ated 604 feasible solutions to implement the LC-VCO.


In this third working example, the design of a LC-VCO aiming a centre oscillation fre-quency of 2.8 GHz was performed. The results obtained with the proposed methodology as well as those obtained through HSPICE (BSIM3v3) and HSPICE RF simulations are offered in Table 6.22. The circuit elements’ sizes are given in Table 6.21.

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Wp (µm)

Wn (µm)

Wb (µm)

w (µm) din

(µm) N turns Shape

W (µm)

L (µm)

Nf

257.8 93.8 187.6 10.50 135.50 2.5 4 357.8 0.46 16


Parameters fosc

(GHz)

L1MHz

(dBc/Hz)

Ibias (mA)

Pdc

(mW)

FoM (dBc/Hz)

Voutamp

(V)

Optim. 2.75 -105.7 2.62 3.15 169.4 0.32

Simulation 2.65 -122.0 2.44 2.93 185.8 0.47

Error (%) 3.8 13.4 7.4 7.5 8.8 31.9



The reported data in Table 6.22 reveals an acceptable accuracy between estimated and simulated results. The errors are quite reasonable and highlight the performance of the pro-posed tool. Regarding the oscillator tuning range, during the optimization design the varactor control voltage was fixed to 0.4 V. Thus, and assuming that the control voltage varies be-

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157

tween 0.2 and 0.8 V, the estimated tuning range is about 17%. Through simulation the oscil-lation frequency for a control voltage of 0.2V was 2.46 GHz, and for 0.8 V was 2.96 GHz, which performs a tunable range of 19%. Furthermore, the DC voltage at nodes Vout and Vx, obtained by simulation were: Vout = 0.74 V and Vx = 0.30 V. The values achieved by the design tool were 0.72 and 0.28 V respectively for Vout and Vx. The design tool during optimi-zation process, has evaluated 2900 (294 feasible solutions) cost functions in 180 seconds.

6.4.3 LC-VCO Hard Approach Optimization

The previously called hard approach optimization considers all the parameters that de-fine the VCO elements’ sizes, as variables to be optimized, and therefore, their value must be estimated. This strategy, increases to number of variables from eight to thirteen, if compared to the previous approach – moderate approach optimization. The additional five variables are the transistors length (Lp, Ln, Lb) and the transistors width (Wp, Wb). In the previous moderate approach design, the length of the transistors were fixed, and the widths, Wp and Wb, were imposed by the width of the transistor NMOS, Wn.

In the hard approach optimization an increment of forty percent in the number of vari-ables is verified. Thus, for the optimization process a population size of 200 individuals was adopted. The maximum population generations was setup to 350, and if the best solution re-mains the same for 25 generations, the algorithm stops. In this section the design of a LC-VCO for operating frequencies of 1.0, 2.0 and 2.8 GHz are considered. The oscillator charac-teristics that are assumed of being fixed, as well as the relation between the transistors widths, during the optimization process are given in Table 6.23.

Table 6.23: LC-VCO design characteristics

Parameters Value

Center frequency - Fosc & ∆f 1.0, 2.0, 2.8 GHz / 1 MHz

Vdd 1.2 V



PMOS transistor width (Wp) 0.5·(β0n/β0p·0.5·Wn) < Wp

Wp < 1.5·(β0n/β0p·0.5·Wn)

NMOS bias transistor width (Wb) 1.5·Wn < Wb < 2.5·Wn


For this first oscillator design, aiming for an oscillation frequency of 1.0 GHz, where the size of the VCO tank and active elements is offered in Table 6.24 and Table 6.25. The re-

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158

sults obtained with the proposed methodology as well as those obtained through HSPICE (BSIM3v3) and HSPICE RF simulations are offered in Table 6.26.

Table 6.24: Resonator’s dimensions (1.0 GHz)



22.75 151.25 5.5 4 459.8 0.46 10

Table 6.25: Active elements size (1.0 GHz)

Active Elements Wp

(µm) Lp

(µm) Wn

(µm) Ln

(µm) Wb

(µm) Lb

(µm)

260.0 0.43 85.8 0.43 175.0 0.35


Parameters fosc

(GHz)

L1MHz

(dBc/Hz)

Ibias (mA)

Pdc

(mW)

FoM (dBc/Hz)

Voutamp

(V)

Optim. 0.97 -122.1 2.70 3.25 176.7 0.49

Simulation 0.94 -127.8 2.35 2.82 182.7 0.58

Error (%) 3.2 4.5 14.9 15.2 3.3 15.5

In all the VCO characteristics shown in Table 6.26, the error rises above the 10% for the parameters that directly depends on the circuit current, such as the power consumption and the output voltage amplitude. This deviation occurs when the transistors length differs from the minimum length adopted for the design process, since the EKV transistor model is strongly dependent on length variation. Regarding the oscillator tuning range, during the opti-mization design the varactor control voltage was fixed to 0.4 V. Thus, and assuming that the control voltage varies between 0.2 and 0.8 V, the estimated tuning range is about 18%. Through simulation the oscillation frequency for a control voltage of 0.2V was 0.91 GHz, and for 0.8 V was 1.05 GHz, which performs a tunable range of 14%.

In Figure 6.17 the VCO output signals of the designed circuit, for an oscillation fre-quency of 1.0 GHz, are presented. The VCO the phase noise characteristic is also illustrated in the same figure. The output signal oscillates between 0.0 and 1.2 V, which represents a full output swing of 1.2 V. Also, at the centre frequency (1.0 GHz), the oscillator phase noise reaches to -127.8 dBc/Hz, in the vicinity of 1 MHz. Regarding the DC voltage at nodes Vout and Vx,, by simulation the values obtained were: Vout = 0.73 V and Vx = 0.29 V. The values achieved by the design tool were 0.71 and 0.30 V respectively for Vout and Vx.

LC-VCO Design

159


For the design of the LC-VCO circuit, the proposed tool took 154 seconds to compute and evaluate 27 populations of 200 individuals each, which has resulted in 546 feasible solu-tions for the design of the oscillator.


This second working example comprises the design of a LC-VCO working at a fre-quency of 2.0 GHz. The LC-VCO devices’ sizes are given in Table 6.27 and Table 6.28, regarding the resonator and active elements, respectively. The results obtained with the pro-posed methodology as well as those obtained through HSPICE and HSPICE RF simulations are offered in Table 6.29.




6.25 160.00 3.5 8 408.8 0.36 13


Active Elements Wp

(µm) Lp

(µm) Wn

(µm) Ln

(µm)

Wb

(µm)

Lb

(µm)

254.8 0.43 84.8 0.45 178.8 0.33

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160


Parameters fosc

(GHz)

L1MHz

(dBc/Hz)

Ibias (mA)

Pdc

(mW)

FoM (dBc/Hz)

Voutamp

(V)

Optim. 1.95 -113.0 2.93 3.51 173.4 0.41

Simulation 1.75 -125.8 2.43 2.92 186.0 0.52

Error (%) 11.4 10.2 20.6 20.2 6.8 17.3

The results presented in Table 6.29 show that the estimated values suffer from the de-pendency of the EKV model on the transistor length. Although, taking advantage of the tun-able varactor, it is possible to change the oscillation frequency to the desired one. The simu-lated circuit shows a tuning range of 18% for a control voltage in the range of 0.2 – 08 V, and for 0.8 V the circuit shows as frequency of 2.05 GHz. The estimated tuning range by the design tool is 15%.

The voltage signal at the output node and the VCO phase noise characteristic are illus-trated in Figure 6.18. In the proposed circuit, the output signal varies between 0.10 and 1.15 V, which represents a tank output swing of 1.05 V. The circuit shows a phase noise of -125.8 dBc/Hz in the vicinity of 1 MHz regarding the LC-VCO oscillation frequency. Regarding the DC voltage at nodes Vout and Vx,, by simulation the values obtained were: Vout = 0.73 V and Vx = 0.28 V. The values achieved by the design tool were 0.70 and 0.30 V respectively for Vout and Vx. For the design of the LC-VCO circuit, the algorithm ran for 196 seconds and evaluated 458 feasible solutions, through 27 generations of a population with 200 individuals.


LC-VCO Design

161


In the last working example, the design of a LC-VCO operating at 2.8 GHz was done. In Table 6.30 and Table 6.31 the sizes of the VCO tank and active elements are presented. The results obtained with the proposed methodology as well as those obtained through HSPICE (BSIM3v3) and HSPICE RF simulations are offered in Table 6.32




25.00 245.25 2.5 6 233.8 0.41 12


Active Elements Wp

(µm) Lp

(µm) Wn

(µm) Ln

(µm)

Wb

(µm)

Lb

(µm)

158.0 0.39 57.8 0.39 141.0 0.39


Parameters fosc

(GHz)

L1MHz

(dBc/Hz)

Ibias (mA)

Pdc

(mW)

FoM (dBc/Hz)

Voutamp

(V)

Optim. 2.66 -110.9 1.97 2.36 175.6 0.49

Simulation 2.63 -117.0 1.80 2.17 182.0 0.43

Error (%) 1.1 5.2 9.4 8.8 3.5 14.0


The reported data in Table 6.32 reveals an acceptable accuracy between estimated and simulated results. Regarding the oscillator tuning range, during the optimization design the varactor control voltage was fixed to 0.4 V. Thus, and assuming that the control voltage var-ies between 0.2 and 0.8 V, the estimated tuning range is about 16%. Through simulation the oscillation frequency for a control voltage of 0.2V was 2.40 GHz, and for 0.8 V was 2.86 GHz, which performs a tunable range of 17%. Furthermore, the DC voltage at nodes Vout and Vx, obtained by simulation were: Vout = 0.71 V and Vx = 0.27 V. The values achieved by the design tool were 0.70 and 0.30 V respectively for Vout and Vx.

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162

The design tool during optimization process, has evaluated 7000 (573 feasible solu-tions) cost functions in 252 seconds.


6.5 Conclusions

The present chapter was devoted to the presentation of the LC-VCO design strategy followed in this work, as well as to show several working example based in different optimiza-tion approaches. The design of a full LC-oscillator supported by a genetic algorithm optimiza-tion methodology, where different approaches regarding what elements to optimize and the number of variables involved, was performed. The design strategy strengths and weaknesses were identified and reported through several comments with respect to the results achieved. In the following three tables the most important characteristics of the designed LC-VCOs are summarized.

By observation of the data reported in the tables below, it can be concluded that the performance of the designed oscillator does not diverge significantly among the different opti-mization approaches. However, when the voltage at nodes Vout and Vx is defined by the de-signer, the simple approach runs ten times faster than the other two. Regarding the LC-VCO implementation area, the inductor is responsible for 98% of the total area. This huge percent-age is mainly due to the wide inner diameter presented by the inductor, which means a lower dependency on the parasitics, regarding the inductor inner turns.

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163

Table 6.33: Overview of the optimization design results vs simulation (1.0 GHz)

Parameters Simple Approach Moderate Approach Hard Approach

Optim. Simul. Optim. Simul. Optim. Simul.

fosc (GHz) 1.00 1.01 1.02 1.07 0.97 0.94

L1MHz (dBc/Hz) -123.2 -126.9 -120.7 -127.1 -122.1 -127.8

Ibias (mA) 1.00 0.95 1.90 1.76 2.70 2.35

Pdc (mW) 1.20 1.13 2.27 2.11 3.25 2.82

FoM (dBc/Hz) 182.5 186.5 177.2 184.4 176.7 182.7

Voutamp (V) 0.39 0.45 0.48 0.59 0.49 0.58

Tuning range (%) 20 24 21 24 18 14

Comput. Time (s) 15 - - - 224 - - - 154 - - -

Area (µm2)

Transistors 676 - - - 687 - - - 573 - - -

Inductor 6.98e4 - - - 20.5e4 - - - 18.0e4 - - -




fosc (GHz) 1.94 1.80 1.90 1.95 1.95 1.75

L1MHz (dBc/Hz) -114.5 -117.9 -113.8 -122.8 -113.0 -125.8

Ibias (mA) 1.00 0.95 1.25 1.16 2.93 2.43

Pdc (mW) 1.20 1.13 1.50 1.39 3.51 2.92

FoM (dBc/Hz) 179.5 182.5 177.6 187.2 173.4 186.0

Voutamp (V) 0.39 0.38 0.45 0.54 0.41 0.52

Tuning range (%) 15 15 20 18 15 18

Comput. Time (s) 16 - - - 145 - - - 196 - - -

Area (µm2)

Transistors 489 - - - 422 - - - 652 - - -

Inductor 8.1e4 - - - 10.5e4 - - - 4.68e4 - - -

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164




fosc (GHz) 2.74 2.48 2.75 2.65 2.66 2.63

L1MHz (dBc/Hz) -111.2 -112.2 -105.7 -122.0 -110.9 -117.0

Ibias (mA) 1.00 0.95 2.62 2.44 1.97 1.80

Pdc (mW) 1.20 1.14 3.15 2.93 2.36 2.17

FoM (dBc/Hz) 179.2 179.5 169.4 185.8 175.6 182.0

Voutamp (V) 0.38 0.30 0.32 0.47 0.49 0.43

Tuning range (%) 15 16 17 19 16 17

Comput. Time (s) 11 - - - 180 - - - 252 - - -

Area (µm2)

Transistors 437 - - - 678 - - - 320 - - -

Inductor 10.3e4 - - - 3.82e4 - - - 14.3e4 - - -

165

7 Conclusions

The progressive scaling of CMOS technology towards nanometre sizes has made pos-sible the implementation of highly integrated systems. Additionally, higher speed, lower power consumption and area reduction has been reached. Due to the high-density integration needs, as well as to low cost fabrication, RF applications, such as the LC-voltage controlled oscillator (LC-VCO), are usually implemented in CMOS technology. The complexity of designing LC-VCOs has lead to the development of several design methodologies. The research on analog simulators as well as on semi-automated CAD tools has been making notorious improve-ments, reducing traditional analog design bottlenecks.

The traditional issue regarding the trade-off between design accuracy and design time are here highlighted. If, on one hand, the requirement to provide a manufacturable device, usually preceded by circuit corrections, makes prohibitive the use of numerical optimizers or fully automated CAD tools; on the other hand, analytical-based systems, usually, run faster, are able to deal with complex circuit design, and are easily adaptable to new “realities”, such as technology processes.

In this dissertation, an optimization based methodology for the design of LC-VCOs was introduced. The meaning of “design” in this work refers to the physical size of each single element in the circuit. The efficiency of the design process is granted by using analytical mod-els to characterize the active and passive elements’ behaviour, which offers an extremely easy adaptability of the design process to new technologies.

The first strength of this work is the use of analytical models to characterize the behav-iour of each circuit element, which allows designers to predict the performance of the full cir-cuit. For that propose, the EKV MOS transistor model either for the characterization of the transistor current behaviour and transconductance characterization, or for the estimation of the transistor capacitances when used as a capacitor, was considered. The EKV model was adopted since its analytical set of equation are mainly based in technological parameters and

Conclusions

166

less in empirical factors. That factor makes the EKV model adaptable when changing between technologies. To comply with this issue, the developed tool includes the extraction process of the EKV model parameters. Furthermore, due to its simplicity, regarding the number of equa-tions, and the characterization of the transistor behaviour from weak to strong inversion re-gions through a single equation, it was shown that the EKV model is fairly suitable to be in-cluded in a circuit design optimization process. Moreover, and being the integrated inductor the main contributor for losses and low quality factor in an oscillator, an analytical model was identified in this work, that accurately characterizes the inductor behaviour, concerning both its inductance and quality factor. The so called double π-model, easily allows to estimate the in-ductor inductance and the quality factor.

The second strength of the present work is the use of evolutionary algorithms, specifi-cally the genetic algorithms, as the path for the optimal design of a full LC-VCO. The optimi-zation methodology adopted in this work, is able to deal with both continuous and discrete variables, making possible to satisfy both technological and layout constraints.

Finally, a set of design examples showing the design of several VCOs for different os-cillation frequencies was considered. It was shown that different strategies can be followed when designing a full LC-VCO, which can go from a wide to a more restricted design. The wide design can be defined from the point of view of the number of variables involved as well as from the freedom given to some voltage and/or current at specific nodes of the circuit. The restricted design, as suggested by the name, refers to a more constrained design, with a smaller search space for feasible solutions, thus, run faster.

In general, the results achieved for the different LC-VCO operating frequencies, have shown a fairly acceptable accordance with those obtained through simulations. Moreover, and in what concerns the figure of merit of the oscillator, the cost function in the optimization pro-cedure, the results produced by the proposed design methodology are in line with those re-ported in published documents in the same field (see Table 2.1).

Through the results depicted in Chapter 6, it was also possible to identify a few weak-nesses in the proposed tool. The main drawback resides in the strong dependency of the EKV model on the variation of the transistors’ length. A not so accurate prediction of the current through the circuit, has a considerable impact on the estimation of its performance. This is easily observable, since the working examples where the average error is around ten per cent, or higher, are the ones where the transistors’ length (active elements) is not in a near vicinity of the minimum length assumed during the optimization process. This drawback maybe overcome with the adoption of the EKV 3.0 but would increase the complexity of the charac-terization.

The feasibility of the obtained design solutions is highlighted via comparison with simu-lated results. Therefore, it is possible to state that the LC-VCO design tool proposed in this

Conclusions

167

dissertation is an adequate analog/RF tool, at least, for a first design approach, avoiding un-feasible design solution. Afterwards, the designer experience and knowledge are valuable skills for a final circuit design.

As a global conclusion, it is our conviction, that evolutionary algorithms, in particular the genetic algorithms, are capable of improving the performance and achieve a feasible design solution of an LC-VCO through an optimization process, that takes into account reliable mod-els of each component, as well as being adaptable to technology changes and takes into ac-count technology/design constrains.

7.1 Summary of Contributions

This research has spotlighted the optimization based design of LC voltage controlled oscillators, by means of evolutionary algorithms. The main contributions of the thesis are briefly summarised as following:

• Identification of an analytical model capable to characterize the behaviour of a tran-sistor in all its regions of operation. The EKV model is also easily adaptable to dif-ferent technologies, since it mainly relies in technological parameters instead of em-pirical or fitting parameters;

• Identification of an analytical model able to characterize the behaviour of an inte-grated inductor. The double-π model has shown to be accurate, and like the EKV model, its analytical model is based in technological and geometric parameters;

• Among several optimization methods, each one appropriated for different scenarios, the GA was chosen and established as the one which generally performed better for the problem under analyses;

• A design tool, at this point restricted for one LC-VCO topology, was proposed. The optimization procedure is capable to deal with both continuous variables and discrete variables, as well as with constraint and unconstraint design problems;

• The use of accurate compact device models, allied to efficient optimization process, makes the determination of the design parameters very rapid, from 101 to a few 102 seconds.

7.2 Suggestions for Future Work

The work developed in this thesis presents many areas which can be further investi-gated in order to improve the design of LC-VCOs circuits. Suggestions for future work as a follow-on to the work presented in this thesis include the following topics.

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168

The accuracy of the analytical models is essential for a correct prediction of the circuit behaviour. Thus, an improvement to the used EKV transistor model, taking into account the effect of large length variations should be addressed, namely by adopting the EKV 3.0. This issue will also drive the designer to adopt a more complex characterization of the parasitic capacitances.

In respect to the integrated inductor analytical model, a step towards the use of models that considers multi-layers inductors should be done. From the point of view of manufacturing an integrated inductor, a more reduced implementation area is achieved with a multi-layer to-pology rather than a single metal layer topology. Although, the complexity of the analytical model should also increase, as it must account for the correlation of several parasitics effects that appears between metal layers.

Finally, additional features aiming a friendly interaction to the user could be added to the developed tool. Firstly, an interface where is given the possibility to introduced the design specifications and constraints is essential. Secondly, the visualization of the feasible search space could provide a deeper insight into the circuit design, allowing designers to adjust the design solution according to personal experience. However, the design computation time might increase.

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179

Appendix I

181

Consider 12

0 ZZZ M−=α , 02

1 ZZZ M−=β and 01 ZZM+=δ

The circuit admittance matrix [ ]Y , with [ ] [ ] [ ]IYU =⋅ , is given by

++−

−++−−

−++−

+

++

+

−⋅⋅

−⋅

+⋅⋅

−

−−⋅⋅

−++

++⋅⋅

+

−⋅

−−−

⋅+

⋅−

⋅−−++−

−⋅

−−−++

+

SubRscCoxRsc

RscmidSubRscmidCoxRscmidCox

RscSubRscCoxCox

M

M

MMMM

midCox

M

midCoxCc

M

M

Cc

MMM

Cox

M

Cc

CoxCs

Cc

ZZZZ

ZZZZZZ

ZZZZZ

ZZZ

ZZZ

ZZZ

ZZ

ZZ

ZZ

Z

ZZZZ

ZZZ

ZZZ

ZZZ

Z

ZZ

ZZ

ZZZ

Z

ZZZ

ZZZ

Z

111100000

112110100

011110001

00011

1111

0101112

1111

000111111

0011111

11

___

2

2

1

1

2

00

00011

_00

_0

20

20

01202

1

α

β

βδ

βαα

βδβ

δβδ

ββ

βαβββαα

ααα

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