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Lecture 3 - 1 PYKC Nov-27-09 E4.20 Digital IC Design
Topic 3
CMOS Fabrication Process
Peter Cheung Department of Electrical & Electronic Engineering
Imperial College London
URL: www.ee.ic.ac.uk/pcheung/ E-mail: [email protected]
Lecture 3 - 2 PYKC Nov-27-09 E4.20 Digital IC Design
Layout of a Inverter
vo
Qp
Qn
VDD
GND
vi
Lecture 3 - 3 PYKC Nov-27-09 E4.20 Digital IC Design
The CMOS Process - photolithography (1)
Silicon Wafer
Silicon Wafer
SiO2 ~ 1μm
Silicon Wafer
photoresist
(a) Bare silicon wafer
(b) Grow Oxide layer
(c) Spin on photoresist
Lecture 3 - 4 PYKC Nov-27-09 E4.20 Digital IC Design
The CMOS Process - photolithography (2)
Silicon Wafer
(d) Expose resist to UV light through a MASK
Silicon Wafer
(e) Remove unexposed resist
Silicon Wafer
(f) Etch away oxide
Silicon Wafer
(g) Remove remaining resist
Lecture 3 - 5 PYKC Nov-27-09 E4.20 Digital IC Design
Mask 1: N-well Diffusion
p-substrate
n-well
p-substrate
Phosphorous Diffusion
SiO2
• SiO2 is etched using Mask 1.
• Phosphorous is diffused into the unmasked regions of silicon creating an n-well for the fabrication of p-channel devices
Lecture 3 - 6 PYKC Nov-27-09 E4.20 Digital IC Design
Mask 2: Define Active Regions
• Mask 2 creates the active regions where the MOSFETs will be placed
• The thick oxide regions provides isolation between the MOSFETs
p-substrate
n-well
SiO2 Photoresist
p-substrate
n-well
SiO2
A thick field oxide is grown using a contruction technique called Local Oxidation Of Silicon (LOCOS).
Photoresist
Lecture 3 - 7 PYKC Nov-27-09 E4.20 Digital IC Design
Mask 3: Polysilicon Gate
• A high quality thin oxide is grown in the active area (~100A->300A)
• Mask 3 is used to deposit the polysilicon gate (most critical step)
The polysilicon layer is usually arsenic doped (n-type). The photolithography in this step is the most demanding since it requires the finest resolution to create the narrow MOS channels.
p-substrate
n-well
SiO2 Thin Oxide
p-substrate
n-well
SiO2
Lecture 3 - 8 PYKC Nov-27-09 E4.20 Digital IC Design
Mask 4: n+ Diffusion
• Mask 4 is used to control a heavy arsenic implant and create the source and drain of the n-channel devices.
• This is a self-aligned structure. p-substrate
n-well
SiO2 Photoresist
Arsenic Implant
p-substrate
n-well
SiO2 n+ n+
The polysilicon gate acts like a barrier for this implant to protect the channel region.
n+
Lecture 3 - 9 PYKC Nov-27-09 E4.20 Digital IC Design
Mask 5: p+ Diffusion
• Mask 5 is used to control a heavy Boron implant and create the source and drain of the n-channel devices.
• This is a self-aligned structure. p-substrate
n-well
SiO2 Photoresist
Boron Implant
p-substrate
n-well
SiO2 n+ n+
The polysilicon gate acts like a barrier for this implant to protect the channel region.
p+ p+ p+ n+
Lecture 3 - 10 PYKC Nov-27-09 E4.20 Digital IC Design
Mask 6: Contact Holes
• A thin layer of oxide is deposited over the entire wafer
• Mask 6 is used to pattern the contact holes
• Etching opens the holes.
Etched contact holes
p-substrate
n-well
SiO2 n+ n+ p+ p+ p+ n+
p-substrate
n-well
SiO2 n+ n+ p+ p+ p+ n+
oxide
Lecture 3 - 11 PYKC Nov-27-09 E4.20 Digital IC Design
Mask 7: Metalization
• A thin layer of aluminum is evaporated or sputtered onto the wafer.
• Mask 7 is used to pattern the interconnection.
p-substrate
n-well
SiO2 n+ n+ p+ p+ p+ n+
p-substrate
n-well
SiO2 n+ n+ p+ p+ p+ n+
Aluminum Interconnection
Lecture 3 - 12 PYKC Nov-27-09 E4.20 Digital IC Design
Cross section of a CMOS Inverter
n+ p+ p+ p+ n+ n+
p-substrate
n-well
VDD
vi vo
Qp Qn
Source-Body Connection Source-Body
Connection
Lecture 3 - 13 PYKC Nov-27-09 E4.20 Digital IC Design
Physical Layout of an Inverter
n-well
PMOS active region
NMOS active region
n+ diffusion
Poly 1 (poly-Si gate)
Metal 1
Contact Hole
p+ diffusion vo
Qp
Qn
VDD
GND
vi
Lecture 3 - 14 PYKC Nov-27-09 E4.20 Digital IC Design
Dimension of transistors
W
L
n+ n+ Poly
L
W p+ p+
n-well
n-channel MOSFET p-channel MOSFET
Poly
Source
Gate
Drain Source
Gate
Drain
Lecture 3 - 15 PYKC Nov-27-09 E4.20 Digital IC Design
Photo cross-section of a transistor
Lecture 3 - 16 PYKC Nov-27-09 E4.20 Digital IC Design
Advanced metalization with polishing
Lecture 3 - 17 PYKC Nov-27-09 E4.20 Digital IC Design
Latch-up problem (1)
As shown above, the p+ region of the p-transistor, the n-well and the p- substrate form a parasitic pnp transistor T1.
The n- well, the p- substrate and the p+ source of the n-transistor forms another parasitic npn transistor T2.
There exists two resistors Rw and Rs due to the resistive drop in the well area and the substrate area.
Lecture 3 - 18 PYKC Nov-27-09 E4.20 Digital IC Design
Latch-up (con’t)
T1 and T2 form a thyristor circuit. If Rw and/or Rs are not 0, and for some
reason (power-up, current spike etc), T1 or T2 are forced to conduct, Vdd will be shorted to Gnd through the small resistances and the transistors.
Once the circuit is 'fired', both transistors will remain conducting due to the voltage drop across Rw and Rs. The only way to get out of this mode is to turn the power off.
This condition is known as latch-up. To avoid latch-up, substrate-taps (tied to
Gnd) and well-taps (tied to Vdd) are inserted as frequently as possible. This has the effect of shorting out Rw and Rs.