João Miguel Morgado Pereira Vieira

PhD Candidate in Electrical and Computer Engineering at Instituto Superior TécnicoRua Francisco Almeida Grandella, n116, Tagarro • 2065–224, Alcoentre • Azambuja, Lisboa, Portugal

+351 91 341 99 77 • joaomiguelvieira@tecnico.ulisboa.ptjoaomiguelvieira.com • linkedin.joaomiguelvieira.com

github.joaomiguelvieira.com

Gender: Masculine • Birth date: April 9th, 1995 (25 years old)

IEEE Student Member: 95073316 • ORCID: 0000-0003-0038-2830

I obtained an MSc degree in Electrical and Computer Engineering from Instituto Superior Técnico (IST),University of Lisbon, Portugal, in November 2018. Starting in my second year of MSc at IST, I have performedseveral research assistantships at institutions of great prestige such as Instituto de Engenharia de Sistemas eComputadores - Investigação e Desenvolvimento (INESC-ID), Lisbon, Portugal, Swiss Institute of TechnologyLausanne (EPFL), Switzerland, and the University of Utah, Salt Lake City, Utah, USA. I am now pursuing aPh.D. in Electrical and Computer Engineering at IST.

EducationInstituto Superior Técnico ISTPh.D. in Electrical and Computer Engineering Feb. 2020–Now

Instituto Superior Técnico ISTIntegrated MSc in Electrical and Computer Engineering Sep. 2013–Nov. 2018BSc GPA: 16/20 [180 ECTS]; MSc GPA: 18/20 [120 ECTS] (Dissertation: 19/20)

Escola Secundária de Azambuja ESEC AzambujaSciences and Technologies course Sep. 2010–Jun. 2013GPA: 18/20

. . . . Test of English as a Foreign Language – Internet Based Test (TOEFL iBT), Nov. 2018Reading Listening Speaking Writing Total

0 30

30

0 30

30

0 30

23

0 30

27

0 120

110

. . . . . . . . . . . . . . . . . . . . . . . . . . . .General Record Examination – General Test (GRE), Oct. 2018Verbal Reasoning Quantitative Reasoning Analytical Writing

130 170

155

69th Percentile

130 170

163

83rd Percentile

0 6

3.0

17th Percentile

*The percentile represents the percentage of test takers who obtained scores lower than the specified score.

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Publications

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . International Journals[2019] J. Vieira, R. P. Duarte, H. Neto, “kNN-STUFF: kNN STreaming Unit For Fpgas”, IEEE Access. Avail-able in https://ieeexplore.ieee.org/document/8911384.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . International Conferences[2020] J. Vieira, N. Roma, G. Falcao, and P. Tomás, “Processing Convolutional Neural Networks onCache”, on 45th International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2020),May 2020, Barcelona, Spain.

[2019] J. Vieira, E. Giacomin, Y. Mahmood Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, and P.-E.Gaillardon, “A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using ResistiveMemories”, on 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC),October 2019, Cusco, Peru.

[2018] J. Vieira, P. Ienne, N. Roma, P. Tomás, and G. Falcao, “Exploiting Compute Caches for MemoryBound Vector Operations”, on International Symposium on Computer Architecture and High PerformanceComputing (SBAC-PAD), September 2018, Lyon, France.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .National Conferences[2020] J. Vieira, “Playing BlokusDuo in a ZYNQ Device: A Quest for an Efficient Algorithm”, on XVI Jor-nadas sobre Sistemas Reconfiguráveis (REC’2020), February 2020, Lisbon Portugal.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Book Chapters[2020] J. Vieira, E. Giacomin, Y. Mahmood Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, and P.-E.Gaillardon, “Accelerating Inference on Binary Neural Networks with Digital RRAM Processing”, VLSI-SoC:EDA the New Technology Enabler, pp. 257–278, Springer, 2020.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Patents[2020] P.-E. Gaillardon, E. Giacomin, J. Vieira, “Digital RRAM-Based Convolutional Block,” United Statespatent application US20200098428A1. March 26, 2020.

Previous EmploymentDepartment of Electrical and Computer Engineering’s Computer Laboratory SCDEECSystem administrator Oct. 2015–Feb. 2018As a system administrator, it was my responsibility to care for the computer laboratory and guaranteethat all the systems were working properly. This experience gave me practice in the area of system andnetwork administration. The domain I have administrated was constituted by both Linux and Windowssystems. I was firstly hired as a monitor. However, I became system administrator in February 2016.

Research ActivitiesINESC-ID INESC-IDResearch Assistant Oct. 2019–Jan. 2020I am a grant owner for project SARROCA, “Synthetic Aperture Radar Robust Reconfigurable OptimizedComputing Architecture”.

University of Utah LNIS | UofUResearch Assistant Jan. 2019–Aug. 2019My research in the Laboratory for NanoIntegrated Systems (LNIS) involved the creation of custom Func-tional Units to be integrated with General Purpose CPUs aiming at accelerating complex Machine Learn-ing applications, such as Convolutional Neural Networks (CNNs). I used the architectural simulator

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gem5 to emulate a modified ARM core, including a state-of-the-art RRAM-based in-memory process-ing module to perform binary matrix convolutions. Such architecture can efficiently run XNOR-Nets, abinary version of CNNs very useful in the context of edge devices.

INESC-ID INESC-IDResearch Assistant Jul. 2018–Dec. 2018I developed near-cache processing structures, by designing wide vector processing units, integratingthem into conventional cache hierarchies and validating their performance for memory-bound kernels.This research complemented the project of my master thesis.

Processor Architecture Laboratory | EPFL LAP | EPFLIntern Feb. 2018–Sep. 2018I have done an internship at the Processor Architecture Laboratory (LAP) at the Swiss Institute of Tech-nology Lausanne (EPFL), Switzerland. This work was supervised by my MSc advisers and ProfessorPaolo Ienne, and its main goal was to develop an architecture of a system to perform computationnear-cache, implement it using VHDL, and create an architectural model for simulation purposes.

INESC-ID INESC-IDIntern Jul. 2015–Sep. 2015The goal of this short-term internship was to modify a simulator of the MIPS architecture to optimize thecontrol path of the CPU. For that purpose, I studied and used several methods to solve data hazards suchas implementing delay slots, performing branch optimization, or applying branch prediction techniques.

LanguagesPortuguês . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (10/10)Nativo

English . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (110/120)Proficient - TOEFL iBT

Deutsch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (4/14)Ein klein Bisschen–Goethe-Institut, Referenzniveau A2.2

Digital Skills

Digital Systems DesignHardware-Software Co-Design

Embedded Systems DevelopmentAlgorithms OptimizationApplications Parallelization Computer Systems Administration

Network Design and ManagementSoftware DevelopmentWeb Development

Database Design

Full Stack

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Programming Languages and Frameworks

Java . . . . . . . . . . . . . . . . . (7/10)C . . . . . . . . . . . . . . . . . . . . (9/10)C++ . . . . . . . . . . . . . . . . . (5/10)Arduino . . . . . . . . . . . . . . (6/10)CUDA . . . . . . . . . . . . . . . . (5/10)LabVIEW. . . . . . . . . . . . . (6/10)Python. . . . . . . . . . . . . . .(7/10)JavaScript . . . . . . . . . . . (4/10)

jQuery . . . . . . . . . . . . . . . (5/10)PHP. . . . . . . . . . . . . . . . . . (9/10)Laravel . . . . . . . . . . . . . . (8/10)Ruby. . . . . . . . . . . . . . . . . (3/10)Matlab . . . . . . . . . . . . . . . (7/10)Bash. . . . . . . . . . . . . . . . . (7/10)VHDL . . . . . . . . . . . . . . . . (8/10)Verilog. . . . . . . . . . . . . . .(4/10)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Digital CompetencesOffice Productivity: Microsoft Office (Word, Excel, PowerPoint), LATEX

Graphical Editing: Adobe Suite (Illustrator, Photoshop, Premiere), Inkscape

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Computer-Aided Design (CAD): Google SketchUp

Integrated Development Environments (IDEs): Eclipse, JetBrains

Web Development: HTML, CSS, MySQL

Operating Systems: Windows (user’s perspective), Linux and macOS (user’s point of view and knowl-edgeable about programming primitives, such as processes, threads, and synchronizationmechanisms)

Domain-specific Tools: SPICE (PSPICE, LTspice), Xilinx Vivado, gem5

Other Relevant ActivitiesIST’s Department of Electrical and Computer Engineering DEEC | ISTAssistant Nov. 2017–Feb. 2018As an associate student of the Department of Electrical and Computer Engineering (DEEC), I hadmultiplefunctions within the department. Namely, one of my tasks was to develop a robust framework to writeand publish content to be displayed in two monitors standing in front of department’s entrance. I wasalso responsible for organizing a workshop about video editing and for developing an HTML frameworkto automatize the deployment of the department’s newsletter.

Instituto Superior Técnico Student Council’s IT Team AEISTSystem administrator Nov. 2017–Nov. 2018Concealingmy knowledge in system administration and cross-boundary emotional intelligence, I helpedto develop means to support the rest of the organization in their daily tasks. I contributed to redesignthe network of this institution, built and installed new machines, and set up support services, such asOpenVPN, a new gateway based on IPFire and a KVM Hypervisor.

Jornadas de Engenharia Eletrotécnica e de Computadores’s IT Team JEEC’18Web Developer Jun. 2017–Apr 2018Jornadas de Engenharia Eletrotécnica e de Computadores (JEEC) brings companies from all over toIST. Students are informed about opportunities in their areas and many end up meeting their futureemployers. In this context, I have developed a platform where students can submit their resumes. Atthe end of the event, these resumes were delivered to the companies. A demo of the platform can befound here.

Instituto Superior Técnico Pedagogical Council CP | ISTExecutive member Feb. 2017–Feb. 2018This organism is responsible for standing and improving the teaching and research qualities of theschool. The pedagogic council is a crucial organism inside IST and the functions I was charged withconstituted a great responsibility. I integrated the committee of the curricular units’ quality, which isresponsible to maintain the high teaching standards of IST.

HackerSchool HackerSchoolMember Sep. 2016–Nov. 2018HackerSchool is an independent organization formed by students whose objective is to develop andbuild original projects and also organize interesting activities not only for the academic community ofIST but also for all those who are interested in areas such electronics, computer science, and robotics.

Instituto Superior Técnico’s Student Support Unit NAPEMentor of younger students Sep. 2015–Feb. 2018As mentor, my job consisted in helping the new students to adapt to the academic life. I worked withfirst grade students as well as Erasmus students.

Volunteering[Nov. 2016, Nov. 2017] I have participated in Web Summit (2016 and 2017 editions) as a volunteer.As I became part of the support team, I was to serve the necessities of the other volunteers and providethem with the tools they needed.

[2013–now] I do volunteering in three parishes. It does not mean a regular responsibility, it is rathersome casual work that is done when it is needed. Usually it consists in religious journals that aredelivered to people during the mass. Sometimes I also produce some posters to announce fundraisings.

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Awards[2019] Certification of excellence for my academic results (level A) given by Instituto Superior Técnico

[2019] Distinguished with a scholarship by my town’s Mayor duo to my academic results

[2018] Certification of excellence for my academic results (level A) given by Instituto Superior Técnico

[2017] 3rd place in EBEC Lisbon, category “Case Study”, organized by BEST Lisbon and sponsored byMcKinsey&Company

[2017] Distinguished with a scholarship by my town’s Mayor duo to my academic results

[2017] Certification of excellence for my academic results (level A) given by Instituto Superior Técnico

[2016] Certification of merit for my academic results (level B) given by Instituto Superior Técnico

[2015] Certification of merit for my academic results (level B) given by Instituto Superior Técnico

[2014] Distinguished with a scholarship by my town’s Mayor duo to my academic results

[2013] Prize Ágora in Demostraciones de Química in the 14th edition of Ciencia en Acción

[2013] 1st place in Demostraciones de Química in the 14th edition of Ciencia en Acción

[2013] Honourable mention in the 21st edition of “Jovens Cientistas Investigadores”

[2010–2013] Certification of merit for my academic results in High School

HobbiesComputer Assembly: Since I was very young I was curious about electronics, more specifically, thecomputer’s internal structure. By disassembling old computers, assembling them back again and evenmodifying them in the process, I made this a hobby, one that I yet keep.

RTL Design: Nowadays, High Level Synthesis (HLS) is gaining popularity over Register Transfer Level(RTL) design since it allows to easily create hardware accelerators from plain C functions. On the otherhand, the circuitry obtained with RTL design, in general, wins by area and performance to those pro-duced by HLS. I described multiple hardware accelerators using RTL description and VHDL. This is anarea that interests me and became one of my favourite subjects.

Linux administration and networkmanagement: As a system administrator since February 2016, I aminto Linux based systems administration and I am interested to learn evenmore to get into development.I am interested in taking courses such as those offered by Linux Foundation and Red Hat in this topic.

Web Design: Despite of being a beginner in this matter, I am actively improving my skills and learning ahigh level framework, Laravel, for PHP. As far as static content is accepted, my knowledge about HTML,CSS, JavaScript and PHP is enough to produce fairly complex websites.

3D Printing: In summer 2016 I have acquired and assembled a kit of a 3D printer, the helloBEEprusa.I am fascinated with this subject and I have already made it a hobby of mine. I have designed numer-ous basic objects using CAD, essentially to fit in my other projects, since very specific parts (such asenclosures) are often needed for electronic projects.

Example Projects

Java Interactive Black Jack game: Project details and implementation can be found in https://web.tecnico.ulisboa.pt/~joaomiguelvieira/public/projects/videopoker/. A full report of the project can alsobe found in https://web.tecnico.ulisboa.pt/~joaomiguelvieira/public/docs/reports/videopoker.pdf.

Laravel IST Space Management Platform: Project details and implementation can be found in https://istspaceman.joaomiguelvieira.com/. A full report of the project can also be found in https://web.tecnico.ulisboa.pt/~joaomiguelvieira/public/docs/reports/istspaceman.pdf.

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VHDL kNN-STUFF: kNNSTreamingUnit for Fpgas: IEEE Access article can be found in https://ieeexplore.ieee.org/document/8911384. Project implementation can be found in https://github.com/joaomiguelvieira/kNN-STUFF.

C kNNSim: k-Nearest Neighbors Simulator: Project implementation can be found in https://github.com/joaomiguelvieira/KNNSim.

ReferencesReferences are available on request.

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