A Control Technique to Eliminate Irregular Current and Voltage Pulses in Resonant DC Link Power Converters

R. C. Castanheira, B. J. Cardoso Fo., B. R. Menezes, P. Donoso Garcia, and A. F. Moreira

Centro de Pesquisa e Desenvolvimento em Engenharia Elehica Universidade Federal de Minas Gerais

Rua Espirito Santo, 35 - 30. andar - 30.160-030 - Belo Horizonte, MG - Brazil Fax: (055) (03 1) 448-5480 - E.Mai1: DONGAR@BRUFMG.BITNET

Abstract - Resonant DC link power conversion circuits can experience irregular current or voltage pulses due to abrupt changes in the voltage or current that excites the resonant link. This paper presents a control technique to eliminate these irregular pulses in both. series and parallel resonant link converters without any additional switch or passive component, resulting in pulses with uniform amplitude. This technique is not restricted to any particular modulation strategy and leads naturally to a design methodology. Experimental results are presented.

INTRODUCTION

Series and parallel resonant DC link power converters can experience irregular high peak current or voltage pulses due to abrupt changes in the voltage or current that excites the resonant link. As a result, higher switch ratings are required and control stability can even be compromised. The occurrence of such irregular pulses have been reported in the literature for both parallel [1][2] and series [3][4] resonant DC link converters.

Without any clamping, regular peaks in the basic topologies reach approximately 2.5 times the DC bias current or voltage, while the irregular peaks can reach an amplitude two or three times greater than that of the regular ones. The amplitude of the regular pulses is a problem too, because the switching devices will need a higher rating than that necessary in conventional hard switched inverters. This has motivated the development of clamping circuits [2]-[6] utilizing additional switches and passive components. To account for the irregular pulses, in general large passive clamping components are required with some added control complexity.

This paper presents a control technique to eliminate these irregular peaks, resulting in pulses with uniform amplitude, no matter the change in the voltage or current that excites the resonant link. The technique can be applied to both parallel and series resonant DC link conveiters and leads to a simple switching law. As applied to the basic topologies, pulse amplitudes are uniformly limited to about 2.5 times the DC bias, without any additional switch or passive component. Its extension to the control of the actively clamped parallel resonant DC link converter (ACPRDCL), presented in [2], allows pulse amplitudes of about 1.2-1.4 pu with a low clamping capacitance and simple control.

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This technique is not restricted to any particular modulation strategy because only the instant of switching is controlled and no restrictions are imposed on which devices are to be switched. It was derived fkom a geometric analysis of trajectories in the resonant circuit phase plane, and leads naturally to a design methodology.

PROBLEM STATEMENT

The technique is derived for the parallel resonant DC link converter, for which experimental results will be presented. By duality, it can be extended to the series resonant DC link converter.

The basic topology of the parallel resonant DC link converter (PRDCL) as proposed by Divan [I] is shown in figure 1. Its principle of operation has been described in [ 1][2].

IL IX

Vd = rJg7* Figure 1. Parallel resonant DC link converter

IL -+ T I

To load

Figure 2. PRDCL convertcr equivalent circuit

In all the following analysis, the PRDCL converter is considered ideal, i.e., losses are neglected. Its equivalent circuit is shown in figure 2, where Zx represents the current that excites the resonant link, considered constant during a resonant cycle. The dynamic behavior of the circuit can be described by arcs of

0-7803-18.59-5/94/$4.00 ' 1994 IEEE

circle in a phase plane plot relating ZOIL to Vc (Zo = J../c(l is the characteristic impedance), centered at (Vd , Zolx), as shown in figure 3, for two different excitation currents, Ix = I I and Ix = 1 2 . When the link voltage goes to zero, that is, when the trajectory crosses the ZOIL axis, all switches are turned on and the inductor current rises linearly. At some instant, three out of six switches are turned-off in zero voltage switching and the cycle restarts, with a new excitation current determined by a particular switching configuration.

I

Figure 3 . Irregular pulse in PRDCL converter

Figure 3 shows in solid lines the phase plane plot corresponding to two different excitation voltages. When the conducting phase changes, the resonant link experiences generally an abrupt change in the excitation current I x . If the transition is from cycle A to cycle B, that is, when occurs an increase in the excitation current, the circuit goes through the A+B trajectory, corresponding to an increase in the inductor current rise time. No overvoltage nor overcurrent are observed. However, when the switching pattern determines a reduction in the excitation current, trajectoiy B+A occurs and veiy high current and voltage peaks can result.

PROPOSED CONTROL TECHNIQUE - PRDCL CONTROL

Two-arcs law

The maximum excitation current that can be applied to the resonant link equals the load line peak current; let it be denoted by Ip. The proposed control technique consists in the following: switches should be turned-off (stating the resonant mode) at the instant when the difference between IL and the next excitation current, determined by h i s particular switching, Ix', equals Ip. Doing so, not only irregular pulses will not occur no matter the excitation current change, but the pulses will have constant and uniform amplitude.

Figure 4 shows the limit case of a transition from Ix = +Ip to Ix = -Ip, when switch turn-off occurs immediately after the end of the resonant mode corresponding to Ix = +Ip, and the trajectories intercept at the origin. It is important to note that

the difference /L - Ix' = Ip is made constant for every Ix', so pulse amplitudes for any other transition will be exactly the same.

ZOIL

LoILpeak

zoIpQ

-+ "c V c p k

Figure 4. Phase plane plot for the Two-arcs law

So, the control law (Two-arcs law) is:

turn-off switches when I L ( ~ ) - Ix' 2 /p . The next excitation current Ix+ is obtained from the

knowledge of the next inverter switching pattem, determined by some modulation strategy, and from the measured load currents.

The control of the inductor current at the beginning of the resonant pulse as a means to limit voltage pulse amplitude has been presented by Lai and Bose in [9]. Their main idea is much similar to that presented here, but two important differences must be pointed out:

i ) in [9], the difference I L ( ~ ) - Ix' was made constant to about 0.3Ip, a value determined for a parhcular characteristic impedance. As a result, trajectories corresponding to Ix = +Ip and Ix = -Ip do not intercept on the ZOIL axis, requiring an extra current initialization circuit with two additional active devices (and associated control complexity) to introduce a linear mode in which inductor current de.c,reases. However, the voltage stress and the excursion of inductor current during the linear mode are minimum;

ii) no design methodology was presented for the characteristic impedance Zo, which could be chosen with some arbitrariness. As it will be presented in the following, the proposed design methodology for the Two-arcs control law has a similar degree of arbitrariness in the choice of angle CL (shown in figure 4) which indirectly determines 20. However, the authors believe that designing with angle CL gives a better insight into voltage aiid current stresses and relates more directly to the effect of losses on circuit stability.

7hree-arcs law

A noticeable reduction in current stress over inductor Lo can be accomplished by inserting a free-wheeling cycle between the extreme cycles of Ix = +/p and Ix = - Ip , as shown in figure 5 . The free-wheeling cycle is obtained by turning-on three switches on the upper or lower rail.

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Now the control law (Three-arcs law) is:

(i) if IL( to) - Ix+ 2 I p / 2 , insert a free-wheeling cycle;

(ii) turn-off switches when I L ( t ) - Ix' 2 Ip/2 where I ~ ( t o ) denotes the inductor current immedialeh after the end of the resonant mode (i.e., at zero voltage crossing). At this instant, for every cycle, condition (i) is tested and, after its evaluation, one waits for condition (ii) to turn-off three out of the six switches. Condition (i) eventually change the switching pattern (Ix'=O), but it does not determine an immediate switch turn-off, i.e., one always waits for condition (ii) to turn-off switches.

Law I Topology Two-arcs

Three-arcs

ZOIL m

Monophase Three-phase 1.50 pu 1.17 pu 1.25 pu 1.00 pu

n LolLpeaA

h ' P

VC

U Figure 5 . Phase plane plot for the Three-arcs law

The inductor current stress is reduced from approximately 2Ip for the Two-arcs law to approximately I.5Ip for the Three- arcs law, a 25% improvement which will be reflected essentially in the reduction of the inductor ESR losses.

A modified CAM has been proposed in [7] as a means of selecting the zero voltage vector (zero state) to avoid reversal of the excitation current. This selection is done by the Three-arcs control law when it inserts a free-wheeling cycle.

A drawback of the proposed control technique is related to switch current stress in the linear mode, when all switches are closed. Considering an equal load cuirent distribution over two switches on the same inverter a n n and an equal resonant inductor cument distribution over all arms, the switch cuirent stress can be summarized as in table 1.

Table 1. Switch current stress

It is seen that for the three phase topoloby, controlled according to the Three-arcs law, no cuirent stress penalty is imposed on inverter switches

~~

DESIGN METHODOLOGY - PRDCL

The proposed design methodology arises naturally from the phase plane analysis. Given Vu! (DC bias voltage), ip (load peak current), f (switching frequency) and the angle a (shown in

figure 4), design consists in determining:

Vd t a n a zo =- AIL

where AIL is given by

1 )

l p , for the Two - arcs law ( 2 ) @/2, for the Three- arcs taw

3) CO is obtained from (4)

The angle a is determined as a trade-off between voltage and current stresses,

= ~ p + A I I , ~ I + cot2 a (5)

(6) FCiCpeok = Vd (1 + J+tan2a) This design was obtained in this simple form because losses

were ignored. The inductor ESR loss and device losses impose a limit on the minimum angle CI which, if exceeded, prevents the bus voltage zero crossing. On the phase plane plot, losses cause trajectories to degenerate into convergent spirals. Unfoitunately, losses will not be considered in this first approach to a design methodology. As a reasonable trade-off between stresses and the effect of losses, the angle a can be chosen typically between 45-60 degrees.

CONTROL OF THE ACTIVELY CLAMPED P m C L

The actively clamped parallel resonant DC link converter (ACPRDCL) as proposed by Divan and Skibinski [ 2 ] is shown in figure 6. Its equivalent circuit is shown in figure 7 .

Vd L

T To load

Figure 6 Actively clamped parallel resonant DC link convertcr

c c sc

L I I

Figure 7 ACPRDCL converter equivalent circuit

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Control of the clamping switch Sc and the effect of clamping can be visualized in figure 8. At point 1 in figure 8(a), switch Sc is opened and the control law turns-off inverter switches. The resonant link becomes excited by a current Ix, as a result of a particular inverter configuration and load currents. The circuit goes through trajectoxy 1-2 with a characteristic

impedance Zo =,/- until Vc reaches Vd, the DC bias voltage. Without clamping, the dotted trajectoxy 2-3 would occur, but at this point switch Sc is turned-on (the antiparallel diode conducts first), changing the characteristic impedance to

Zc = d m , Zc < Zo, so that the cycle jumps to the point 2' on the phase plane relating ZCZL to Vc, in figure S(b). The circuit goes through trajectory 2'-3' until Vc reaches Vd again, when Sc is turned-off in a lossless manner. Circuit jumps back to point 3 on the phase plane relating Zoh to Vc , in figure 8(a), and the resonant mode ends at point 4 when the link voltage goes to zero. The inductor current IL increases linearly through trajectory 4- 1 and the cycle restarts.

Since Zc < 20, the trajectory 2'-3' can be represented in the phase plane plot of figure 8(a) as the solid 2-3 trajectory, an arc of ellipsis, where it becomes clear the effectiveness of the clamping circuit in reducing the voltage stress.

m ZOIL

I ' V ,

ZCIL

' Vd Vcpeak vc

Figure 8. Actively clamped PRDCL converter phase plane plot

With the clamping circuit so controlled, the extension of the Two-arcs and Three-arcs laws to the control of the ACPRDCL involves no modification to the laws, which are exactly the same, but only to the design methodology. Its important to note that the clamping capacitor actually participates on a new resonant mode of lower frequency, rather than being a constant (and controlled) voltage source. As a consequence, no net charge is transferred to the capacitor during a resonant cycle, so that its voltage at the beginning and at the end of the clamping mode are equal to zero. Control of the clamping switch Sc is simple and involves only a comparison between the link voltage, Vc, and the DC bias voltage, Vd. Since there is no need of clamp voltage regulation, the clamping capacitance has a value lower than that which has been reported in the literature. In fact, its value is uniquely determined by design specifications such as switching frequency and clamping factor.

DESIGN METHODOLOGY - ACPRDCL

Given Vd (DC bias voltage), Ip (load peak current), J (switching frequency), k (clamping factor),

and the angle a (shown in figure 4), deteimining :

V~penk = (1 + k)Vd

Z0=- Vd t ana A I L

1)

where AIL is given by (2).

3)

k . Zo

zc=Jizz

(7) design consists in

(9)

1 i7-2a i7 2AIL]-' f [ zo ZC Vd

L o = - ~ +--+-

4) CO and Cc are obtained from

The current stress over inductor LO is given by (5). Again, losses wcrc ignored. Since the voltage stress is limited by design, one could set a large CL to reduce current stress, as given by (5). But higher values of ct implies in higher values of C k , as given by (9) and (1 l), so a trade-off must be considered.

The ratio between the clamping capacitance and the resonant capacitance can be obtained as

1 cc - l + t a n 2 a CO k 2

Figure 9 shows an abacus where the above ratio can be found as a function of the clamping factor k and the angle a. Given a desired clamping factor, design with a low a value results in a reduced C c K o ratio, at the expense of increased current stress and reduced stability (as a consequence of inevitable losses).

1

c c C O -

0 0 1 0 2 0 3 0 4 0 5 06 07 0 8 0 9 I k

Figure 9. Abacus relating CC/CQ to k for a varying from 30" to 70'

A limit on the minimum angle a is imposed by component and device losses. As a reasonable trade-off, the angle a can be chosen typically between 45-60 degrees.

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EXPERIMENTAL RESULTS

The main objective of the experimental results obtained is to prove the effectiveness of the proposed control technique in eliminating irregular pulses in a parallel resonant DC link converter. The worst condition for occurrence of irregular pulses is that of a complete reversal of the excitation current. This condition is easily reproduced in a monophase topology of the PRDCL converter, shown in figure 10, supplying an inductive load with a constant load current reference equals to the maximum designed load current, I m d = Ip.

Vd Lload

Figure 10. Monophase actively clamped PRDCL converter

Results will be shown for two different designs: a basic topology of the PRDCL (Cc opened) with Two-arcs control law and an actively clamped PRDCL with Three-arcs control law. Design parameters are given below:

V d = 5 O V , I p = 2 A , f=30kHz , a=45" , k = 0 . 3

PRDCL - Two-arcs law ACPRLICL - Three-arcs law Zc = 10.6 Tr Zo = 50 Cl

Lo = 124 pH CO = 198 nF

Vcpeak= 121 V ILpeak = 4.8 A

Zo = 25 Cl Lo = 90.6 p.H CO = 36.3 nF Cc = 0.77 pF Vcpeak = 65 V ILpeak = 3.4 A

Current regulation was done by means of a CRAM [8] with a load inductance of LLOAD = 20 mH. Inductor and load current were measured by hall effect current sensors. MOSFET's were utilized as switches. An analog multiplexer selected by the current regulator informs the next excitation current IX' to a comparator which dnves the control logic.

Figures 1 1 to 13 show the results of interest for the PRDCL design (no clamping, Two-arcs control law). As it can be seen, cunent and voltage stresses agree very well with the expected values. To account for inductor ESR (0.21C2 @ IkHz), parameter AIL. was increased by 10% to maintain trajectories intercepting at the phase plane origin.

Figures 14 to 16 show similar results for the ACPRDCL design (actively clamped, Three-arcs control law). The benefits of the clamping and the free-wheeling cycle insertion are noted as a reduction in voltage and current stresses.

A sinusoidal load current reference is applied to the ACPRDCL converter to verify its behavior when the excitation current varies between extreme values. Figure 17 shows the absence of irregular voltage pulses while figure 18 demonstrates the CRAM performance.

Figure 11. Vc [SOV/div] and IL [4Ndiv] (PRDCL)

Figure 12 Vc [SOV/div] and IL [2A/dv] - XY plot (PRDCL)

~. _ _ _ _ _ _ ~ Figure 13 Vc [SOV/div] and Ix [4A/divj (PRDCL)

L

______.-__

Figure 14 Vc [SOV/div] and IL [2Ndiv] (ACPRDCL)

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L_ __ ~- Figure 15 Vc [SOV/div] __ and IL [ lA/dLj- W-plot (ACPRDCL)

I

I - - ~ _ ____ -~~ Figure 16 Vc [ZOV/div] and IK [ZNdiv] (ACPRDCL)

As it can be seen from (1)-(3) and (8)-( IO), design does not change if Vd and lp are increased by the same factor. So, the component values utilized in the above design are the same for a 300V, 12A ACPRDCL inverter. The clamping capacitor for similarly rated converters has been reported in the literature as

a 50-100 pF capacitance, a value 100 times greater than the obtained according to the proposed control technique and design methodology (('c = 0.77 pF ).

CONCLUSION

The experimental results shown the effectiveness of the proposed control technique in eliminating irregular peaks in a parallel resonant DC link converter, maintaining pulse amplitudes uniform for any change in the excitation current.

Despite the unifonn pulse amplitudes, the voltage stress over switches remains high, approximately at 2 . 5 ~ ~ . Therefore, from a practical point of view, a clamping circuit is still necessary, limiting the shess to I .2- I .4pu. The application of the proposed control technique to the actively clamped PRDCL converter and the resulting pulse unifoimity leads to a designed clamping capacitance which is minimurn in the sense that its value is that exactly necessaiy to limit voltage excursion for a given set of design parameters. Since the net charge hansfeixd into the clamping capacitor during a resonant cycle is always zero, clamping switch control is simple and easy.

The design methodology, presented in a very simple manner, has in angle a a degree of freedom which should be explored as a means of reducing losses. optimizing efficiency and assuring stability.

REFERENCES

[ I ] D. hl. Divan, "The Resonant DC Link Converter--A New Concept in Static Power Conversion", I ('onference Record? 1986, pp. 648-656.

[2] D. M. Divan and G. Skibinski, "Zei Inverters for High-Power Applications". APP//C., IA-25, 1989, pp. 634-643.

[3] Y. Murai and T. A. Lipo, "High Fre DC Link Power Conversion", liecord, 1988, pp, 772-779.

[4] Y. Murai, S. Mochizuki, P. Caldeira and T. A. Lipo, "Cuirent Pulse Control of High Frequency Series Resonant DC Link Power Converter", IEElGL4S Conference Record,

[5] Y. Rdurai, S. G. Abeyratne, T. A. Lip0 and P. Caldeira, "Dual-Flow Pulse Trimming Concept for a Series Resonant DC Link Power Conversion", I Confkrencc Record, 199 1, pp. 254-260.

[6] P. Donoso Garcia and I . Barbi, "A Family of Resonant DC- Link Voltage Source Lnveiters", lE iZ- lE( 'ON ('onjcrence Record, 1990, pp. 844-849.

[7] T. G . Habctler and D. M. Divan, "Performance Characterization of ew Discrete Pulse Modulated Cument Regulator". -[AS ('onfkrence IIecord, 1988,

[SI R. D. Lorentz and D. M. Divan, "Dynamic Analysis and Experimental Evaluation of Delta Modulators for Field Oriented AC Machine Curent Regulators", IEEE-IAS Annual Meeting Conference Hecord, 1987, pp. 196-20 I .

[9] Jih-Sheng Lai and B. K. Bose, "An Improved Resonant DC Link Inverter for Induction Motor Drives", IElX-IAS ('onferencc Kccord, 1988, pp. 742-748.

1989, pp. 1023-1030.

pp. 395-405.

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