psi 2223 – introdução à eletrônica programação para a...

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PSI 2223 – Introdução à EletrônicaProgramação para a Terceira Prova

20ª Aula: Detalhes no funcionamento do MOSFET canal n

Características do MOSFET canal p

Ao final desta aula você deverá estar apto a:

- Explicar efeitos de segunda ordem presentes nas leis do MOSFET

- Distinguir o “MOSFET canal n” do “MOSFET canal p”

- Projetar circuitos para MOSFETS

- Empregar em circuitos as equações do MOSFET

- Analisar circuitos de polarização com transistores FET

2

• Região Triodo: 0< VDS VGS-Vt e VGS>Vt

2

VVVV

L

W kI

2DS

DStGSnD

• Região de Saturação: 0< VGS-Vt VDS e VGS>Vt

2

VV

L

WkI

2tGS

nD

onde oxnox

oxn .Cμx

εμnk

(Parâmetro de Transcondu-tância do processo [A/V2])

Resumindo o NMOSFETNMOSFET

• Região de Corte: VGS Vt ou VGS-Vt 0 ID=0

)(

)(

tGSoxnDS

DStGSoxnD

VvLW

Cr

vVvLW

CI

1

Linear ( se VDS << VGS-Vt )Parabólica

2n(superfície)

2p(superfície)

12

12

μ =450cm /Vsμ =100cm /Vs

0,345 10 /1 10 /

ox

si

F cmF cm

Características de Corrente-Tensão do NMOSFET Tipo Enriquecimento

2

VVVV

L

W kI

2DS

DStGSnD

2

VV

L

WkI

2tGS

nD

VGS>Vt

3

Um Modelo de Circuito para a Região de Saturação

(VDS > VGS − Vt)

Limiar entre triodo e saturação: vDS = vGS - Vt

2

VV

L

WkI

2tGS

nD

Modelo Geral, válido para qualquer sinal (AC ou DC) na região de saturação

Relembrando Exemplo 4.5 Analise o circuito abaixo e determine todas as tensões nos nós e correntes nos ramos.Considere Vt= 1,0 V e kn´=0,02 mA/V2 e (W/L) = 50/1 m/m

EquaEquaçções de Iões de IDD=f(V=f(VGSGS, V, VDSDS) de 1) de 1aa OrdemOrdem

• Região Triodo: 0< VDS VGS-Vt

2

VVVV

L

W kI

2DS

DStGSnD

• Região de Saturação: 0< VGS-Vt VDS

2

VV

L

WkI

2tGS

nD

onde oxnox

oxn .Cμx

εμnk


Resumindo o NMOSFETNMOSFET


)(

)(

tGSoxnDS

DStGSoxnD

VvLW

Cr

vVvLW

CI

1


IG = 05V !!!

4

Exemplo 4.5 Analise o circuito abaixo e determine todas as tensõesnos nós e correntes nos ramos.Considere Vt= 1,0 V e kn´=0,02 mA/V2 e (W/L) = 50/1 m/m

• Região de Saturação: 0< VGS-Vt VDS

2

VV

L

WkI

2tGS

nD

onde oxnox

oxn .Cμx

εμnk


IG = 05V !!!

• Equação da malha de entrada:

5 5GS S D GS S DV V R I V V R I

2

2

(5 )1

2S D t

D

mA V R I VI

V

2 22 22 1 (5 1) 1 (4 6 )D S D D

mA mAI V R I kI

V V

28 25 18 0D DI I

225 25 4 18 8 25 49 25 72 18 36 36DI

2 222 1 (16 48 36 )D D D

mAI kI k I

V

0,89

0,50

mA

mA

0,89 6 5,34 () )(D S D G tGSe I mA V kI V ou V VV

0,5 6 3 10 3 7D S D DSe I mA V kI V e V V

( )7 3 4 DS GS tDS V V V saturaçãV e oV

Supondo na Saturação!

VGS

2GS tD

V VWI k

L 2n

Região de Saturação

VDS > VGS − Vt

Limiar entre triodo e saturação: vDS = vGS - Vt

NMOSna saturação

NMOSVDS fixo!

5

A Resistência de Saída Finita na Saturação(modulação do comprimento de canal)

).V 1(

2

VV

L

WkI DS

2tGS

nD

L DSVcom

1A Ao

D D D

V V VVr

I I I I

DI

TOTALD D DadicionalI I I

TOTAL

DSD D

O

VI I

r

TOTALD D DS DI I V I

1( )TOTALD D DSI I V V

Modelo de circuito equivalente para grandes sinais de

um NMOSFET operando em saturação incorporando r0

AVonde

1

2

12

( . )REAL

GS tD n DS

v VWi k v

L

IDidealizado Do Ir

1

6

Modelo de circuito equivalente para grandes sinais de um

NMOSFET operando em saturação incorporando r0

ADo V

ondeI

r11

Di Dadicionali

Modelo de circuito equivalente para grandes sinais de um NMOSFET operando em saturação incorporando r0

ADo V

ondeI

r11

Região de Saturação: Modelo para grandes sinais

7


• Região Triodo: 0< VDS VGS-Vt e VGS > Vt

2

VVVV

L

W kI

2DS

DStGSnD

• Região de Saturação: 0< VGS-Vt VDS e VGS > Vt

2

GS tD

VWL

1V

I k2 DSn V

onde oxnox

oxn .Cμx

εμnk


NMOSFETNMOSFET


)(

)(

tGSoxnDS

DStGSoxnD

VvLW

Cr

vVvLW

CI

1


2n(superfície)

2p(superfície)

12

12

μ =450cm /Vs

μ =100cm /Vs

0,345 10 /

1 10 /

ox

si

F cm

F cm

O Transistor MOSFET - Canal P (PMOS)

P+ P+

N

Porta(G)Porta(G)

Dreno(D)Dreno(D)Fonte(S)Fonte(S)

Substrato (B)Substrato (B)

8


• Região Triodo: 0< VDS VGS-Vt E VGS > Vt

2

VVVV

L

W kI

2DS

DStGSnD

• Região de Saturação: 0< VGS-Vt VDS E VGS > Vt

2

GS tD

VWL

1V

I k2 DSn V

onde oxnox

oxn .Cμx

εμnk


NMOSFETNMOSFET


)(

)(

tGSoxnDS

DStGSoxnD

VvLW

Cr

vVvLW

CI

1


2n(superfície)

2p(superfície)

12

12

μ =450cm /Vs

μ =100cm /Vs

0,345 10 /

1 10 /

ox

si

F cm

F cm

9

Características de Corrente-Tensão do NMOSFET e do PMOSFET tipo Enriquecimento

PMOS (Vt < 0 !!!) NMOS

VGS>VtVGS<Vt

• Região Triodo: VGS-Vt VDS < 0 e VGS < Vt

2V

VVVLW

kI2

DSDStGSD p

• Região de Saturação: VDS VGS-Vt < 0 e VGS < Vt

PMOSFETPMOSFET


)(

)(

tGSoxpDS

DStGSoxpD

VvLW

Cr

vVvLW

CI

1

Linear ( se VDS << VGS-

Vt )Parabólica

2

GS tD

VWL

1V

I k2 DSp V

onde p oxp ox

ox

μ εμ .C

xpk


VGS , VDS e Vt < 02

n(superfície)

2p(superfície)

12

12

μ =450cm /Vs

μ =100cm /Vs

0,345 10 /

1 10 /

ox

si

F cm

F cm

10

Modelagem do Efeito de Corpo (efeito de 2ª ordem)

Fonte não está no terra, mas substrato está!!!

2

VV

L

WkI

2tGS

nD

???

uma segunda porta...(backgate)

VSB

Um tipo de amplificador

Modelagem do Efeito de Corpo

2

VV

L

WkI

2tGS

nD

]2.V2.[VV fSBft 0t

1/2

ox

2 onde 2 0,6 ; 0,4

CA s

f

qNV V

Tensão de Limiar de CorpoPotencial de superfície

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O Efeito da Temperatura

•Tanto Vt como k’ são sensíveis à temperatura:

•Vt diminui (em módulo) 2mV/°C (ID aumenta)•k’ diminui com a temperatura e é o efeito dominante•Assim, ID DIMINUI com o AUMENTO da temperatura

2V

VVVLW

kI2

DSDStGSD p

Perfil de um Circuito Integrado CMOS

N+ N+P+ P+ P+ N+

P N

N -

N+

NMOS PMOS

B S G D D G S B

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O que está por trás do anúncio da IntelIEEE Spectrum: 9 May 2011— Last Wednesday, Intel announced a big change to the electronic switches at the heart of its CPUs. Goingforward, the firm will be using three-dimensional transistors to take theplace of long-used planar devices.

The new transistors—dubbed "tri-gates"—are a variation on theFinFET, a transistor design that substitutes the flat channel through whichelectrons flow with a 3-D ridge, or fin.

Popping the channel out of plane and draping the gate—which switches the transistor on and off—over it will allow Intel to shrink the smallestfeatures in its transistors from 32 nanometers to 22 nm while cuttingpower consumption in half. This feat would be impossible to dowith the transistor design the company had been using.

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2D 3D

O que está por trás do anúncio da Intel

How did this 3-D design win its way intoproduction?

We asked the coinventor of the FinFET, IEEE Fellow Chenming Hu, a professor emeritus at the University of California, Berkeley, how the new transistors got their start, why we need them now, and where they will go from here.


http://www.eecs.berkeley.edu/~hu/Chenming-Hu_ch5.pdfhttp://www.intel.com/content/www/us/en/energy/intel-22nm-3-d-tri-gate-transistor-technology.html

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IEEE Spectrum: We’ve been shrinking two-dimensional, or planar, transistors just fine for 50 years. Why are we seeing a switch to threedimensional FinFETs?Chenming Hu: I’ll distill the problem with planar transistors to a single point. It all stemsfrom the fact that it is very difficult to turn off a transistor when it’s very small. In otherwords, you can’t stop the current flowing through the transistor when you don’t want thecurrent to flow.I’ll use an analogy to explain this. There is a garden hose lying on a soggy lawn, and youwant to stop the water from flowing into this lawn. If there’s a long hose, you can call yourfriends to come in and put 10 pairs of hands down, andyou can stop the water. Now imagine you shorten the hose so you cannot even put one palm on it to stop it. Now you shorten it even more, so you can only put one finger on it. It’s impossible to stop.In the past 10 years, people have dealt with this garden hose problem in various ways, andone way has been to sacrifice power. For 250-nm transistors, the power-supply voltage was2.5 volts; for 180 nm, it was 1.8 V; for 130 nm, it was 1.3 V. The pattern was very regular until90 nm, but it reached a limit. Instead of 0.9 V, you know what the industry used? 1.2 V. Evenat 45 nm, the industry still used 0.9 V instead of 0.45 V.


IEEE Spectrum: So current is leaking even when the transistors are off. To get around thatproblem, you have to use a higher voltage to make the difference between on and off more obvious?Chenming Hu: Exactly. What’s the consequence of that? Power is proportional to the square of the voltage. So if you use twice as high a voltage as the historical trend, your cellphone will consume four times the power. The pain is just too big to keep going that way. We thought planar technology would run out of steam sometimeafter 25 nm, and it did.

IEEE Spectrum: How do FinFETs help fix the leaky garden hose problem?Chenming Hu: Remember, the hose is on a soggy, soft lawn. So what if instead of pressing your finger on this garden hose, you pinch your fingers on the two sides of the garden hose? That’s the analogy. The weakpoint, the soggy lawn, is the silicon substrate. So you really have to do something on both sides so you’repinching against something firm, an that’s what the FinFET is doing. We should pinch the channel [where electronsflow] on two sides and on top. The more pinching sides, the better.Pinching the hose will allow us to use a much, much shorter hose. That’s extremely important. Making thingssmall is really the key of making the electronics cheaper, faster, and lower power.


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IEEE Spectrum: The idea for FinFETs has been around for a while. How did it all get started?Chenming Hu: DARPA [the Defense Advanced Research Projects Agency] sent out a request for proposals in 1996 for ideas to develop electronic switches beyond 25 nm. At the time, the industry was using 250-nmtransistors, and the general view was that transistors could not be scaled below 100 nm. But my students and I had already been thinking about how to get transistors to scale to 25 nm and beyond.

There was a quick meeting probably lasting only five minutes between myself and two colleagues—ProfessorTsu-Jae King Liu and Professor Jeff Bokor. The meeting was short because we already knew what to do.I was on a flight to a conference in Japan, and I had about 10 hours, so I just wrote down the technical proposal in longhand. I proposed two structures that we’d been thinking about for a while. One was FinFETs, and the other is what we call an ultrathin-body silicon-on-insulator (UTB SOI).We got the contract in 1997, and that gave us the resources to demonstrate FinFETs experimentally. A younggraduate student named Xuejue "Cathy" Huang made the working device, and the team of three professors and11 students and visiting researchers published it in 1999.


O que está por trás do anúncio da IntelPublished: 1999

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IEEE Spectrum: How did the industry react to the FinFET paper?Chenming Hu: It was an instant hit. I remember Cathy and I were invited to Intel Santa Clara just a coupleof months after the publication, and in that same year, 2000, I was invited to Intel Oregon twice. At the time, people were asking me how long it would take for the idea to get into production. I said about 10 years, so I guess I was off by one. ...


psi 2223 – introdução à eletrônica programação para a...

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