j. m. martins ferreira feup / deec - rua dr. roberto frias 4200-537 porto - portugal

Design for Test Seminar @ HIBU – Oct. 31st 2006J. M. Martins Ferreira - University of Porto (FEUP / DEEC)

1

J. M. Martins Ferreira

FEUP / DEEC - Rua Dr. Roberto Frias

4200-537 Porto - PORTUGAL

Tel. 351 225 081 889 / Fax: 351 225 081 443

([email protected] / http://www.fe.up.pt/~jmf)

Overview of the IEEE 1149.x test standards

Design for Test Seminar


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Boundary-scan (1149.1)Mixed-signal (1149.4)AC testing (1149.6)

• Why and where to use?

• The BS test principle

• Test access port and BS architecture

• BS instructions


3

Why Boundary Scan Test?• The two main reasons that led in the mid-

80s to the development of BST were:– The complexity of ICs made it exceedingly

difficult to develop test programs for the functional test of complex PCBs

– Small outline surface mount devices and advanced mounting technologies almost disabled physical access to internal PCB nodes and made in-circuit test exceedingly difficult


4

The application domain of BST• BST addresses the structural test of

digital printed circuit boards

• Keywords: structural, digital, PCBs

• This embedded test infrastructure is now used for other purposes as well (e.g. in-system programming)


5

The BS test principle

• BS uses a Test Access Port (TAP) to decouple the internal IC logic from the pins and allows “direct” access to any PCB node without backdriving effects


6

The BS architecture

• Main blocks:– BST register– BP register– Instruction register– TAP controller– Other registers

User data reg.

Identific. reg.

BP reg.

Decoder

Instruction reg.

Data mux

Data / instr. mux

TAP contr.

TDI

/TRST

TMS

TCK

TDO

BST register


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The basic BS cell

• Three modes of operation:– Transparency– Controllability– Observability

RegistoBST

Serial input

Parallel input

Parallel output

Serial output

mux

mux

C/S L


8

TAP controller state transition diagram1

0

Shift DR

Capture DR

Select DR

Exit-1 DR

Pause DR

Exit-2 DR

Update DR

Test LogicReset

Run Test /Idle

Shift IR

Capture IR

Select IR

Exit-1 IR

Pause IR

Exit-2 IR

Update IR

1

1

1

1

1

1

1

0

0

0

0

0

0

0

1 1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

User data reg.

Identific. reg.

BP reg.

Decoder

Instruction reg.

Data mux

Data / instr. mux

TAP contr.

TDI

/TRST

TMS

TCK

TDO

BST register

Serial input

Parallel input

Parallel output

Serial output

mux

mux

C/S L


9

BST instructions

• Mandatory:– EXTEST– SAMPLE / PRELOAD– BYPASS

• Optional:– INTEST, RUNBIST,

CLAMP, IDCODE,USERCODE, HIGHZ

BST register

BST register

User data reg.

Identific. reg.

BP reg.

Data mux

Data / instr. mux

TDO


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• 1149.4: an extension of 1149.1

• TBIC and ABMs (internal test circuitry)

• The PROBE instruction

• Parametric testing


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• The 1149.4 std defines an extension to 1149.1, to which it adds:– An analog test port (ATAP)

with two pins (AT1, AT2)– An internal analog test bus

(AB1, AB2)– A test bus interface circuit

(TBIC)– The analog boundary

modules (ABM)

The IEEE 1149.4 standard for mixed signal test

BST infrastructure (except the BST register)

TBIC

ABM

DBM

(AB1, AB2)

AT1

AT2

TDI

TMS

TCK

TDO


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The test bus interface circuit (TBIC)• The TBIC defines the interconnections

between the ATAP (AT1 and AT2) and the internal analog test bus (at least two lines, AB1 and AB2)

• The TBIC comprises a switching structure and a control structure


TBIC

ABM

DBM

(AB1, AB2)

AT1

AT2

TDI

TMS

TCK

TDO


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TBIC: The switching structure

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7 S5 S6


TBIC

ABM

DBM

(AB1, AB2)

AT1

AT2

TDI

TMS

TCK

TDO


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TBIC: Control structure


TBIC

ABM

DBM

(AB1, AB2)

AT1

AT2

TDI

TMS

TCK

TDO

Parallel input

Serial input

Serial output

Parallel input

Parallel input

Parallel input

S1 S2 S10

Control logic

Parallel output

Mode

Inputs available to the user VTH VTH

AT1 AT2 Switching structure comparators

Switching structure

Parallel output

Parallel output

Parallel output


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The analog boundary modules (ABM)• The ABMs in the analog pins

extend the test functions made available by the DBMs

• All test operations combine digital (via TAP) and analog test “vectors” (via ATAP)

• Each ABM comprises a switching structure and a control structure


TBIC

ABM

DBM

(AB1, AB2)

AT1

AT2

TDI

TMS

TCK

TDO


16

ABMs: Switching structure

SH SL SG

SB1 SB2

Analog pin

AB2

AB1 VH VL VG VTH

SD

Internal analog block


TBIC

ABM

DBM

(AB1, AB2)

AT1

AT2

TDI

TMS

TCK

TDO


17


TBIC

ABM

DBM

(AB1, AB2)

AT1

AT2

TDI

TMS

TCK

TDO

Parallel input

Serial input

Serial output

Parallel input

Parallel input

Parallel input

SD SH SB2

Control logic

Parallel output

Mode

Inputs available to the user

VTH

Pin

Switching structure comparator

Switching structure

Parallel output

Parallel output

Parallel output

ABMs: Control structure


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The 1149.4 register structure• The 1149.4

register structure is entirely digital and identical to the corresponding 1149.1 structure

User registers

Identification register

Reg. BP

Decoder

Instruction reg.

Data mux

Data / instruction mux

TAP contr.

TDI

/TRST

TMS

TCK

TDO

BST register

TBIC cells

ABM cells

DBM (BST cells in 1149.1)


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The PROBE instruction

• The IEEE 1149.4 std defines a fourth mandatory instruction called PROBE:– The selected data register is the BS register– One or both of the ATAP pins connect to the

corresponding AB1/AB2 internal test bus lines– Analog pins connect to the core and to AB1/AB2

as defined by the ABM 4-bit control word– Each DBM operates in transparent mode


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SH SL SG

SB1 SB2 Analog pin

AB2 AB1

VH VL VG VTH

SD

AT1

AT2

AB1 AB2

VH

VL

VTH

Vclamp

S1

S3

S2

S4 S9 S10

S8 S7S5 S6

Impedance measurement between pin and ground


TBIC

ABM

DBM

(AB1, AB2)

AT1

AT2

TDI

TMS

TCK

TDO

IT

VVT

ZD = VT / IT if:

• ZV >> ZS6 + ZSB2

• ZV + ZS6 + ZSB2 >> ZD

ZD


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• Scope and objectives

• Test of AC-coupled differential networks

• 1149.6 test cells and instructions


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Scope and objectives

• Scope of 1149.6: Structural test of high-speed digital networks

• Objectives– Cope with differential and/or AC-coupled

interconnections, enabling high fault coverage with minimum impact on mission logic

– Reuse as much as possible IEEE 1149.1 tools (ensure compatibility with 1149.1 / 4)


23

AC-coupling, differential signalling

R

011010

Receiver

-

+

Negative

Transmitter

C

Vref

Positive

C

011010

R

• Single-ended signalling with AC-coupling

• Differential signalling with AC-coupling and bias provision

TX:

RX:R

TX

ReceiverTransmitter

RX

C


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Testing AC-coupled / differential networks• BS cell placement has an impact on

circuit performance and defect coverage

• Modified BS cells must ensure:– Signal transmission over AC-coupled nets– Logic level detection from AC test signals

C

Positive

R

R

Receiver

-

+

Transmitter

Vref

C

Negative


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Serial input

Parallel input

Parallel output

Serial output

mux

mux

C/S L

U

Mission 0

AC Mode

AC Signal

01

1

Mode

1149.6 test cells

• An AC testing instruction selects the AC Mode, and a test signal suited for AC-coupled networks is applied to the pin

• A test receiver at the input cell derives logic level information from the incoming AC / DC test signal(valid transitions)

UC

Mode

10

TestReceiver

AC Mode

Mission


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1149.6 instructions

• EXTEST_PULSE generates a transition even when the new test value at the driver pin retains its previous value

• EXTEST_TRAIN provides multiple additional transitions (to cope with transient conditions, when necessary)

• Both cause the driver pins to change state at least twice in Run-Test / Idle

(fro

m a

Gee

k S

quad

add

)

Coffee break

j. m. martins ferreira feup / deec - rua dr. roberto frias 4200-537 porto - portugal

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