datasheet ice3br0665j v2!3!19nov2012

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  • 8/12/2019 Datasheet ICE3BR0665J v2!3!19Nov2012

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    CoolSET-F3R

    ICE3BR0665J

    Off-Line SMPS Current Mode

    Control ler wi th integrated 650V

    CoolMOS and Startup cel l

    ( f requency j i t ter Mode) in DIP-8

    N e v e r s t o p t h i n k i n g .

    Power Management & Supply

    Version 2.3, 19 Nov 2012

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    Edition 2012-11-19

    Published byInfineon Technologies AG,81726 Munich, Germany,

    2012 Infineon Technologies AG.All Rights Reserved.

    Legal disclaimer

    The information given in this document shall in no event be regarded as a guarantee of conditions orcharacteristics. With respect to any examples or hints given herein, any typical values stated herein and/or anyinformation regarding the application of the device, Infineon Technologies hereby disclaims any and all warrantiesand liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rightsof any third party.

    Information

    For further information on technology, delivery terms and conditions and prices, please contact your nearestInfineon Technologies Office (www.infineon.com).

    Warnings

    Due to technical requirements, components may contain dangerous substances. For information on the types inquestion, please contact your nearest Infineon Technologies Office.

    Infineon Technologies Components may be used in life-support devices or systems only with the express writtenapproval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failureof that life-support device or system or to affect the safety or effectiveness of that device or system. Life support

    devices or systems are intended to be implanted in the human body or to support and/or maintain and sustainand/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons maybe endangered.

    For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany orthe Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com

    CoolMOS, CoolSETare trademarks of Infineon Technologies AG.

    CoolSET-F3RICE3BR0665JRevision History: 2012-11-19 Datasheet

    Previous Version: 2.2

    Page Subjects (major changes since last revision)

    27 revised outline dimension for PG-DIP-8 package

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    Type Package Marking VDS FOSC RDSon1)

    1) typ @ Tj=25C

    230VAC 15%2)

    2) Calculated maximum input power rating at Ta=50C, Ti=125C and without copper area as heat sink. Refer to input power curve for other Ta.

    85-265 VAC2)

    ICE3BR0665J PG-DIP-8 ICE3BR0665J 650V 65kHz 0.65 74W 49W

    CoolSET-F3RICE3BR0665J

    Version 2.3 3 19 Nov 2012

    Off-Line SMPS Current Mode Controller withintegrated 650V CoolMOS and Startup cell

    (frequency jitter Mode) in DIP-8

    PG-DIP-8

    Description

    The CoolSET-F3R jitter series (ICE3BRxx65J) is thelatest version of CoolSET-F3. It targets for the Off-Linebattery adapters and low cost SMPS for lower powerrange such as application for DVD R/W, DVD Combi, Blueray DVD player, set top box, etc. Besides inherited theoutstanding performance of the CoolSET-F3 in theBiCMOS technology, active burst mode, auto-restartprotection, propagation delay compensation, etc.,CoolSET-F3R series has some new features such asbuilt-in soft start time, built-in blanking window, built-infrequency jitter, soft gate driving, etc. In case a longerblanking time is needed for high load application, a simpleaddition of capacitor to BA pin can serve the purpose.

    Furthermore, an external auto-restart enable feature canprovide extra protection when there is a need ofimmediate stop of power switching.

    Product Highlights Active Burst Mode to reach the lowest Standby Power

    Requirements < 50mW Auto Restart protection for overload, overtemperature, overvoltage External auto-restart enable function Built-in soft start and blanking window Extendable blanking Window for high load jumps Built-in frequency jitter and soft driving for low EMI Green Mould Compound Pb-free lead plating; RoHS compliant

    Features 650V avalanche rugged CoolMOSwith built-in

    Startup Cell Active Burst Mode for lowest Standby Power Fast load jump response in Active Burst Mode 65kHz internally fixed switching frequency Auto Restart Protection Mode for Overload, Open

    Loop, VCC Undervoltage, Overtemperature &Overvoltage

    Built-in Soft Start Built-in blanking window with extendable blanking

    time for short duration high current External auto-restart enable pin Max Duty Cycle 75%

    Overall tolerance of Current Limiting < 5% Internal PWM Leading Edge Blanking BiCMOS technology provide wide VCC range Built-in Frequency jitter and soft driving for low EMI

    CVCC

    CBulkConverter

    DC Output

    +

    Snubber

    Power Management

    PWM Controller

    Current Mode

    85 ... 270 VAC

    Typical Application

    RSense

    BA

    FB

    GNDActive Burst Mode

    Auto Restart Mode

    Control

    Unit

    -

    CS

    VCC

    Startup Cell

    Precise Low Tolerance Peak

    Current Limitation

    Drain

    CoolSET-F3R

    (Jitter Mode)

    CoolMOS

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    CoolSET-F3R

    ICE3BR0665J

    Table of Contents Page

    Version 2.3 4 19 Nov 2012

    1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

    1.1 Pin Configuration with PG-DIP-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

    1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

    2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

    3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

    3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

    3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

    3.3 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

    3.3.1 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

    3.3.2 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

    3.4 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113.5 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

    3.5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

    3.5.2 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

    3.5.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

    3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

    3.6.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

    3.6.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

    3.7 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

    3.7.1 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .15

    3.7.2 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

    3.7.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

    3.7.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

    3.7.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

    3.7.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

    3.7.3.1 Auto Restart mode with extended blanking time . . . . . . . . . . . . . . . . .17

    3.7.3.2 Auto Restart without extended blanking time . . . . . . . . . . . . . . . . . . .18

    4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

    4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

    4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

    4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

    4.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

    4.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

    4.3.3 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

    4.3.4 Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

    4.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

    4.3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

    4.3.7 CoolMOSSection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

    5 Typical CoolMOSPerformance Characteristic . . . . . . . . . . . . . . . . . . .24

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    CoolSET-F3R

    ICE3BR0665J

    Version 2.3 5 19 Nov 2012

    6 Input Power Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

    7 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

    8 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

    9 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .29

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    Version 2.3 6 19 Nov 2012

    CoolSET-F3R

    ICE3BR0665J

    Pin Configuration and Functionality

    1 Pin Configuration and Functionality

    1.1 Pin Configuration with PG-DIP-8

    Pin Symbol Function

    1 BA extended Blanking & Auto-restart

    2 FB FeedBack

    3 CS Current Sense/

    650V1)

    1) at Tj=110C

    CoolMOSSource

    4 Drain 650V1) CoolMOS Drain

    5 Drain650V

    1)

    CoolMOS

    Drain6 n.c. Not connected

    7 VCC Controller Supply Voltage

    8 GND Controller GrouND

    Package PG-DIP-8

    1

    6

    7

    8

    4

    3

    2

    5

    GNDBA

    FB

    CS

    VCC

    n.c.

    Drain Drain

    Figure 1 Pin Configuration PG-DIP-8 (top view)

    Note: Pin 4 and 5 are shorted

    1.2 Pin Functionality

    BA (extended Blanking & Auto-restart)

    The BA pin combines the functions of extendableblanking time for over load protection and the externalauto-restart enable. The extendable blanking timefunction is to extend the built-in 20 ms blanking time byadding an external capacitor at BA pin to ground. Theexternal auto-restart enable function is an externalaccess to stop the gate switching and force the IC enterauto-restart mode. It is triggered by pulling down theBA pin to less than 0.33V.

    FB (Feedback)The information about the regulation is provided by theFB Pin to the internal Protection Unit and to the internalPWM-Comparator to control the duty cycle. The FB-Signal is the only control signal in case of light load atthe Active Burst Mode.

    CS (Current Sense)

    The Current Sense pin senses the voltage developedon the series resistor inserted in the source of theintegrated CoolMOSIf voltage in CS pin reaches theinternal threshold of the Current Limit Comparator, theDriver output is immediately switched off. Furthermorethe current information is provided for the PWM-Comparator to realize the Current Mode.

    Drain (Drain of integrated CoolMOS)

    Drain pin is the connection to the Drain of theintegrated CoolMOS.

    VCC (Power Supply)

    VCC pin is the positive supply of the IC. The operatingrange is between 10.5V and 25V.

    GND (Ground)

    GND pin is the ground of the controller.

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    Version 2.3 8 19 Nov 2012

    CoolSET-F3R

    ICE3BR0665J

    Functional Description

    3 Functional DescriptionAll values which are used in the functional description

    are typical values. For calculating the worst cases themin/max values which can be found in section 4Electrical Characteristics have to be considered.

    3.1 Introduction

    CoolSET-F3R jitter series (ICE3BRxx65J) is the latestversion of the CoolSET-F3 for the lower powerapplication. The particular enhanced features are thebuilt-in features for soft start, blanking window andfrequency jitter. It provides the flexibility to increase theblanking window by simply addition of a capacitor in BApin. In order to further increase the flexibility of theprotection feature, an external auto-restart enablefeatures are added. Moreover, the proven outstandingfeatures in CoolSET-F3 are still remained such as theactive burst mode, propagation delay compensation,modulated gate driving, auto-restart protection for Vccovervoltage, over temperature, over load, open loop,etc.

    The intelligent Active Burst Mode can effectively obtainthe lowest Standby Power at light load and no loadconditions. After entering the burst mode, there is still afull control of the power conversion to the outputthrough the optocoupler, that is used for the normalPWM control. The response on load jumps is optimizedand the voltage ripple on Voutis minimized. The Voutison well controlled in this mode.

    The usually external connected RC-filter in thefeedback line after the optocoupler is integrated in theIC to reduce the external part count.

    Furthermore a high voltage Startup Cell is integratedinto the IC which is switched off once the UndervoltageLockout on-threshold of 18V is exceeded. This StartupCell is part of the integrated CoolMOS. The externalstartup resistor is no longer necessary as this StartupCell is connected to the Drain. Power losses aretherefore reduced. This increases the efficiency under

    light load conditions drastically.Adopting the BiCMOS technology, it can increase thedesign flexibility as the Vcc voltage range is increasedto 25V.

    The CoolSET-F3R has a built-in 20ms soft startfunction. It can further save external componentcounts.

    There are 2 modes of blanking time for high loadjumps; the basic mode and the extendable mode. Theblanking time for the basic mode is set at 20ms whilethe extendable mode will increase the blanking time byadding an external capacitor at the BA pin in addition to

    the basic mode blanking time. During this blanking timewindow the overload detection is disabled. With thisconcept no further external components are necessaryto adjust the blanking window.

    In order to increase the robustness and safety of the

    system, the IC provides Auto Restart protection. TheAuto Restart Mode reduces the average powerconversion to a minimum level under unsafe operatingconditions. This is necessary for a prolonged faultcondition which could otherwise lead to a destruction ofthe SMPS over time. Once the malfunction is removed,normal operation is automatically retained after thenext Start Up Phase. To make the protection moreflexible, an external auto-restart enable pin is provided.When the pin is triggered, the switching pulse at gatewill stop and the IC enters the auto-restart mode afterthe pre-defined spike blanking time.

    The internal precise peak current control reduces the

    costs for the transformer and the secondary diode. Theinfluence of the change in the input voltage on themaximum power limitation can be avoided togetherwith the integrated Propagation Delay Compensation.Therefore the maximum power is nearly independenton the input voltage, which is required for wide rangeSMPS. Thus there is no need for the over-sizing of theSMPS, e.g. the transformer and the output diode.

    Furthermore, this F3R series implements thefrequency jitter mode to the switching clock such thatthe EMI noise will be effectively reduced.

    3.2 Power Management

    Internal Bias

    Voltage

    Reference

    Power Management

    5.0V

    Undervoltage Lockout18V

    10.5V

    Power-Down Reset

    Active Burst

    Mode

    Auto Restart

    Mode

    Startup Cell

    VCCDrain

    Depl. CoolMOS

    Soft Start block

    Figure 3 Power Management

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    CoolSET-F3R

    ICE3BR0665J

    Functional Description

    Version 2.3 9 19 Nov 2012

    The Undervoltage Lockout monitors the externalsupply voltage VVCC. When the SMPS is plugged to themain line the internal Startup Cell is biased and starts

    to charge the external capacitor CVCC which isconnected to the VCC pin. This VCC charge current iscontrolled to 0.9mA by the Startup Cell. When the VVCCexceeds the on-threshold VCCon=18V the bias circuitare switched on. Then the Startup Cell is switched offby the Undervoltage Lockout and therefore no powerlosses present due to the connection of the Startup Cellto the Drain voltage. To avoid uncontrolled ringing atswitch-on, a hysteresis start up voltage is implemented.The switch-off of the controller can only take placewhen VVCC falls below 10.5V after normal operationwas entered. The maximum current consumptionbefore the controller is activated is about 150A.

    When VVCCfalls below the off-threshold VCCoff=10.5V,the bias circuit is switched off and the soft start counteris reset. Thus it is ensured that at every startup cyclethe soft start starts at zero.

    The internal bias circuit is switched off if Auto RestartMode is entered. The current consumption is thenreduced to 150A.

    Once the malfunction condition is removed, this blockwill then turn back on. The recovery from Auto RestartMode does not require re-cycling the AC line.

    When Active Burst Mode is entered, the internal Bias isswitched off most of the time but the Voltage Reference

    is kept alive in order to reduce the current consumptionbelow 450A.

    3.3 Improved Current Mode

    x3.3

    PWM OP

    Improved

    Current Mode

    0.67V

    C8

    PWM-Latch

    CS

    FBR

    S

    Q

    Q

    Driver

    Soft-Start Comparator

    Figure 4 Current Mode

    Current Mode means the duty cycle is controlled by theslope of the primary current. This is done by comparingthe FB signal with the amplified current sense signal.

    t

    FB

    Amplified Current Signal

    ton

    t

    0.67V

    Driver

    Figure 5 Pulse Width Modulation

    In case the amplified current sense signal exceeds theFB signal the on-time Tonof the driver is finished byresetting the PWM-Latch (see Figure 5).

    The primary current is sensed by the external seriesresistor RSense inserted in the source of the integratedCoolMOS. By means of Current Mode regulation, thesecondary output voltage is insensitive to the linevariations. The current waveform slope will change withthe line variation, which controls the duty cycle.

    The external RSenseallows an individual adjustment ofthe maximum source current of the integratedCoolMOS.

    To improve the Current Mode during light loadconditions the amplified current ramp of the PWM-OPis superimposed on a voltage ramp, which is built bythe switch T2, the voltage source V1 and a resistor R1

    (see Figure 6). Every time the oscillator shuts down formaximum duty cycle limitation the switch T2 is closedby VOSC. When the oscillator triggers the Gate Driver,T2 is opened so that the voltage ramp can start.

    In case of light load the amplified current ramp is toosmall to ensure a stable regulation. In that case theVoltage Ramp is a well defined signal for thecomparison with the FB-signal. The duty cycle is thencontrolled by the slope of the Voltage Ramp.

    By means of the time delay circuit which is triggered bythe inverted VOSCsignal, the Gate Driver is switched-offuntil it reaches approximately 156ns delay time (seeFigure 7). It allows the duty cycle to be reduced

    continuously till 0% by decreasing VFB below thatthreshold.

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    PWM OP

    0.67V

    10k

    Oscillator

    C8

    T2 R1

    C1

    FB

    PWM-Latch

    V1

    Gate Driver

    Voltage Ramp

    VOSC

    Soft-Start Comparator

    time delay

    circuit (156ns)

    X3.3

    PWM Comparator

    CoolSET-F3R

    ICE3BR0665J

    Functional Description

    Version 2.3 10 19 Nov 2012

    Figure 6 Improved Current Mode

    t

    t

    VOSC

    0.67V

    FB

    t

    max.Duty Cycle

    Gate Driver

    Voltage Ramp

    156ns time delay

    Figure 7 Light Load Conditions

    3.3.1 PWM-OP

    The input of the PWM-OP is applied over the internal

    leading edge blanking to the external sense resistorRSenseconnected to pin CS. RSenseconverts the sourcecurrent into a sense voltage. The sense voltage isamplified with a gain of 3.3 by PWM OP. The output ofthe PWM-OP is connected to the voltage source V1.The voltage ramp with the superimposed amplifiedcurrent signal is fed into the positive inputs of the PWM-Comparator C8 and the Soft-Start-Comparator (seeFigure 6).

    3.3.2 PWM-Comparator

    The PWM-Comparator compares the sensed currentsignal of the integrated CoolMOSwith the feedbacksignal VFB(see Figure 8). VFBis created by an externaloptocoupler or external transistor in combination withthe internal pull-up resistor RFBand provides the loadinformation of the feedback circuitry. When theamplified current signal of the integrated CoolMOS

    exceeds the signal VFBthe PWM-Comparator switchesoff the Gate Driver.

    X3.3

    PWM OP

    Improved

    Current Mode

    PWM Comparator

    CS

    Soft-Start Comparator

    5V

    C8

    0.67V

    FB

    Optocoupler

    RFB

    PWM-Latch

    Figure 8 PWM Controlling

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    3.4 Startup Phase

    Soft-Start

    C om para to r

    Sof t S tar t

    &

    G 7

    C 7Gate Dr iver

    0 .67V

    x3.3

    P W M O P

    C S

    Soft Start counter

    Sof t S tar t

    SoftStartfinish Sof tS

    Figure 9 Soft Start

    In the Startup Phase, the IC provides a Soft Startperiod to control the primary current by means of a dutycycle limitation. The Soft Start function is a built-in

    function and it is controlled by an internal counter..

    VSoftS

    VSoftS2

    VSoftS1

    Figure 10 Soft Start Phase

    When the VVCCexceeds the on-threshold voltage, theIC starts the Soft Start mode (see Figure 10).

    The function is realized by an internal Soft Start

    resistor, an current sink and a counter. And theamplitude of the current sink is controlled by thecounter (see Figure 11).

    5V

    RSoftS

    Soft Start

    Counter

    I2I4I

    SoftS

    8I32I

    Figure 11 Soft Start Circuit

    After the IC is switched on, the VSFOFTS voltage iscontrolled such that the voltage is increased step-

    wisely (32 steps) with the increase of the counts. TheSoft Start counter would send a signal to the currentsink control in every 600us such that the current sinkdecrease gradually and the duty ratio of the gate driveincreases gradually. The Soft Start will be finished in20ms (tSoft-Start) after the IC is switched on. At the end ofthe Soft Start period, the current sink is switched off.

    t

    VSOFTS32

    VSoftS

    Gate

    Driver

    t

    tSoft-Start

    Figure 12 Gate drive signal under Soft-Start Phase

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    Within the soft start period, the duty cycle is increasingfrom zero to maximum gradually (see Figure 12).

    In addition to Start-Up, Soft-Start is also activated at

    each restart attempt during Auto Restart.

    t

    t

    VSoftS

    t

    VSOFTS32

    4.0V

    tSoft-Start

    VOUT

    VFB

    VOUT

    tStart-Up

    Figure 13 Start Up Phase

    The Start-Up time tStart-Upbefore the converter outputvoltage VOUTis settled, must be shorter than the Soft-Start Phase tSoft-Start(see Figure 13).

    By means of Soft-Start there is an effectiveminimization of current and voltage stresses on theintegrated CoolMOS, the clamp circuit and the outputovershoot and it helps to prevent saturation of thetransformer during Start-Up.

    3.5 PWM Section

    Oscillator

    Duty Cycle

    max

    Gate Driver

    0.75

    Clock

    &

    G9

    1

    G8

    PWM Section

    FF1

    R

    S

    Q

    Soft Start

    Comparator

    PWM

    Comparator

    Current

    Limiting

    CoolMOS

    Gate

    Frequency

    Jitter

    Soft StartBlock

    Figure 14 PWM Section Block

    3.5.1 Oscillator

    The oscillator generates a fixed frequency of 65KHzwith frequency jittering of 4% (which is 2.6KHz) at a

    jittering period of 4ms.

    A capacitor, a current source and current sink whichdetermine the frequency are integrated. In order toachieve a very accurate switching frequency, thecharging and discharging current of the implementedoscillator capacitor are internally trimmed. The ratio ofcontrolled charge to discharge current is adjusted to

    reach a maximum duty cycle limitation of Dmax=0.75.Once the Soft Start period is over and when the IC goesinto normal operating mode, the switching frequency ofthe clock is varied by the control signal from the SoftStart block. Then the switching frequency is varied inrange of 65KHz 2.6KHz at period of 4ms.

    3.5.2 PWM-Latch FF1

    The output of the oscillator block provides continuouspulse to the PWM-Latch which turns on/off theintegrated CoolMOS. After the PWM-Latch is set, it isreset by the PWM comparator, the Soft Startcomparator or the Current -Limit comparator. When it is

    in reset mode, the output of the driver is shut downimmediately.

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    3.5.3 Gate Driver

    VCC

    1

    PWM-Latch

    CoolMOS

    Gate Driver

    Gate

    Figure 15 Gate Driver

    The driver-stage is optimized to minimize EMI and toprovide high circuit efficiency. The switch on speed isslowed down before it reaches the integratedCoolMOSturn on threshold. That is a slope control ofthe rising edge at the output of the driver (see Figure16).

    t

    (internal)

    VGate

    5V

    ca. t = 130ns

    Figure 16 Gate Rising Slope

    Thus the leading switch on spike is minimized.Furthermore the driver circuit is designed to eliminatecross conduction of the output stage.

    During power up, when VCC is below the undervoltagelockout threshold VVCCoff, the output of the Gate Driveris set to low in order to disable power transfer to thesecondary side.

    3.6 Current Limiting

    Current Limiting

    C10

    C12

    &

    0.34V

    Leading

    EdgeBlanking

    220ns

    G10

    Propagation-Delay

    Compensation

    Vcsth

    Active Burst

    Mode

    PWM LatchFF1

    10k

    D1

    1pF

    PWM-OP

    CS

    Figure 17 Current Limiting Block

    There is a cycle by cycle peak current limiting operationrealized by the Current-Limit comparator C10. Thesource current of the integrated CoolMOSis sensedvia an external sense resistor RSense. By means ofRSense the source current is transformed to a sensevoltage VSense which is fed into the CS pin. If the voltageVSenseexceeds the internal threshold voltage Vcsth,thecomparator C10 immediately turns off the gate drive byresetting the PWM Latch FF1.

    A Propagation Delay Compensation is added tosupport the immediate shut down of the integratedCoolMOSwith very short propagation delay. Thus theinfluence of the AC input voltage on the maximumoutput power can be reduced to minimal.

    In order to prevent the current limit from distortionscaused by leading edge spikes, a Leading EdgeBlanking is integrated in the current sense path for thecomparators C10, C12 and the PWM-OP.

    The output of comparator C12 is activated by the GateG10 if Active Burst Mode is entered. When it isactivated, the current limiting is reduced to 0.34V. Thisvoltage level determines the maximum power level in

    Active Burst Mode.

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    3.6.1 Leading Edge Blanking

    t

    VSense

    Vcsth

    tLEB

    = 220ns

    Figure 18 Leading Edge Blanking

    Whenever the integrated CoolMOS

    is switched on, aleading edge spike is generated due to the primary-side capacitances and reverse recovery time of thesecondary-side rectifier. This spike can cause the gatedrive to switch off unintentionally. In order to avoid apremature termination of the switching pulse, this spikeis blanked out with a time constant of tLEB= 220ns.

    3.6.2 Propagation Delay Compensation

    In case of over-current detection, there is alwayspropagation delay to switch off the integratedCoolMOS. An overshoot of the peak current Ipeak is

    induced to the delay, which depends on the ratio of dI/dt of the peak current (see Figure 19).

    t

    ISense

    ILimit

    tPropagation Delay

    IOvershoot1

    Ipeak1

    Signal1Signal2

    IOvershoot2Ipeak2

    Figure 19 Current Limiting

    The overshoot of Signal2 is larger than of Signal1 dueto the steeper rising waveform. This change in theslope depends on the AC input voltage. PropagationDelay Compensation is integrated to reduce theovershoot due to dI/dt of the rising primary current.Thus the propagation delay time between exceedingthe current sense threshold Vcsthand the switching offof the integrated CoolMOS is compensated over

    temperature within a wide range. Current Limiting isthen very accurate.

    For example, Ipeak = 0.5A with RSense= 2. The currentsense threshold is set to a static voltage level Vcsth=1Vwithout Propagation Delay Compensation. A current

    ramp of dI/dt = 0.4A/s, or dVSense/dt = 0.8V/s, and apropagation delay time of tPropagation Delay =180ns leadsto an Ipeakovershoot of 14.4%. With the propagationdelay compensation, the overshoot is only around 2%(see Figure 20).

    0,9

    0,95

    1

    1,05

    1,1

    1,15

    1,2

    1,25

    1,3

    0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2

    with compensat ion without compensat ion

    dt

    dVSense

    s

    V

    Sense

    V

    V

    Figure 20 Overcurrent Shutdown

    The Propagation Delay Compensation is realized bymeans of a dynamic threshold voltage Vcsth(see Figure21). In case of a steeper slope the switch off of the

    driver is earlier to compensate the delay.

    t

    Vcsth

    VOSC

    Signal1 Signal2

    VSense Propagation Delay

    max. Duty Cycle

    off time

    t

    Figure 21 Dynamic Voltage Threshold Vcsth

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    3.7 Control Unit

    The Control Unit contains the functions for Active Burst

    Mode and Auto Restart Mode. The Active Burst Modeand the Auto Restart Mode both have 20ms internalBlanking Time. For the Auto Restart Mode, a furtherextendable Blanking Time is achieved by addingexternal capacitor at BA pin. By means of this BlankingTime, the IC avoids entering into these two modesaccidentally. Furthermore those buffer time for theoverload detection is very useful for the application thatworks in low current but requires a short duration ofhigh current occasionally.

    3.7.1 Basic and Extendable Blanking Mode

    C3

    4.0V

    C4

    4.0V

    C5

    1.35V

    &

    G5

    &

    G6

    0.9V

    S1

    1

    G2

    Control Unit

    Active

    Burst

    Mode

    Auto

    Restart

    Mode

    5.0VBA

    FB

    CBK

    20msBlanking

    Time

    20ms

    Blanking

    Time

    Spike

    Blanking

    30us

    # IBK

    Figure 22 Basic and Extendable Blanking Mode

    There are 2 kinds of Blanking mode; basic mode andthe extendable mode. The basic mode is just aninternal set 20ms blanking time while the extendablemode has an extra blanking time by connecting anexternal capacitor to the BA pin in addition to the pre-set 20ms blanking time. For the extendable mode, thegate G5 is blocked even though the 20ms blanking timeis reached if an external capacitor CBKis added to BApin. While the 20ms blanking time is passed, the switchS1 is opened by G2. Then the 0.9V clamped voltage atBA pin is charged to 4.0V through the internal IBKconstant current. G5 is enabled by comparator C3.

    After the 30us spike blanking time, the Auto RestartMode is activated.

    For example, if CBK= 0.22uF, IBK= 13uA

    Blanking time = 20ms + CBKx (4.0 - 0.9) / IBK= 72ms

    In order to make the startup properly, the maximum CBKcapacitor is restricted to less than 0.65uF.

    The Active Burst Mode has basic blanking mode onlywhile the Auto Restart Mode has both the basic and theextendable blanking mode.

    3.7.2 Active Burst Mode

    The IC enters Active Burst Mode under low loadconditions. With the Active Burst Mode, the efficiencyincreases significantly at light load conditions while stillmaintaining a low ripple on VOUTand a fast response onload jumps. During Active Burst Mode, the IC iscontrolled by the FB signal. Since the IC is alwaysactive, it can be a very fast response to the quickchange at the FB signal. The Start up Cell is kept OFFin order to minimize the power loss.

    C4

    4.0V

    C6a

    3.5V

    C5

    1.35V

    FB

    Control Unit

    Active

    Burst

    Mode

    Internal Bias

    &G10

    Current

    Limiting

    &

    G6

    C6b

    3.05V

    &

    G11

    20 ms Blanking

    Time

    Figure 23 Active Burst Mode

    The Active Burst Mode is located in the Control Unit.Figure 23 shows the related components.

    3.7.2.1 Entering Active Burst Mode

    The FB signal is kept monitoring by the comparator C5.During normal operation, the internal blanking timecounter is reset to 0. Once the FB signal falls below1.35V, it starts to count. When the counter reach 20ms

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    and FB signal is still below 1.35V, the system entersthe Active Burst Mode. This time window prevents asudden entering into the Active Burst Mode due to

    large load jumps.After entering Active Burst Mode, a burst flag is set andthe internal bias is switched off in order to reduce thecurrent consumption of the IC to approx. 450uA.

    It needs the application to enforce the VCC voltageabove the Undervoltage Lockout level of 10.5V suchthat the Startup Cell will not be switched onaccidentally. Or otherwise the power loss will increasedrastically. The minimum VCC level during Active BurstMode depends on the load condition and theapplication. The lowest VCC level is reached at no loadcondition.

    3.7.2.2 Working in Active Burst Mode

    After entering the Active Burst Mode, the FB voltagerises as VOUT starts to decrease, which is due to theinactive PWM section. The comparator C6a monitorsthe FB signal. If the voltage level is larger than 3.5V, theinternal circuit will be activated; the Internal Bias circuitresumes and starts to provide switching pulse. In

    Active Burst Mode the gate G10 is released and thecurrent limit is reduced to 0.34V, which can reduce theconduction loss and the audible noise. If the load atVOUTis still kept unchanged, the FB signal will drop to3.05V. At this level the C6b deactivates the internal

    circuit again by switching off the internal Bias. The gateG11 is active again as the burst flag is set after enteringActive Burst Mode. In Active Burst Mode, the FBvoltage is changing like a saw tooth between 3.05V and3.5V (see figure 24).

    3.7.2.3 Leaving Active Burst Mode

    The FB voltage will increase immediately if there is ahigh load jump. This is observed by the comparator C4.Since the current limit is app. 34% during Active BurstMode, it needs a certain load jump to rise the FB signalto exceed 4.0V. At that time the comparator C4 resetsthe Active Burst Mode control which in turn blocks the

    comparator C12 by the gate G10. The maximumcurrent can then be resumed to stabilize the VOUT.

    1.35V

    3.5V

    4.0V

    VFB

    t

    t

    0.34V

    1.03V

    VCS

    10.5V

    VVCCt

    t

    450uA

    IVCC

    t

    3.8mA

    VOUT

    t

    20ms Blanking Time

    Current limit level

    during Active Burst

    Mode

    3.05V

    Entering

    Active Burst

    Mode

    Leaving

    Active Burst

    Mode

    Blanking Timer

    Figure 24 Signals in Active Burst Mode

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    3.7.3 Protection Modes

    The IC provides Auto Restart Mode as the protectionfeature. Auto Restart mode can prevent the SMPS from

    destructive states. The following table shows therelationship between possible system failures and thecorresponding protection modes.

    VCC Overvoltage Auto Restart Mode

    Overtemperature Auto Restart Mode

    Overload Auto Restart Mode

    Open Loop Auto Restart Mode

    VCC Undervoltage Auto Restart Mode

    Short Optocoupler Auto Restart Mode

    Auto restart enable Auto Restart Mode

    Before entering the Auto Restart protection mode,some of the protections can have extended blankingtime to delay the protection and some needs to fastreact and will go straight to the protection. Overloadand open loop protection are the one can haveextended blanking time while Vcc Overvoltage, Overtemperature, Vcc Undervoltage, short opto-couplerand external auto restart enable will go to protectionright away.

    After the system enters the Auto-restart mode, the IC

    will be off. Since there is no more switching, the Vccvoltage will drop. When it hits the Vcc turn off threshold,the start up cell will turn on and the Vcc is charged bythe startup cell current to Vcc turn on threshold. The ICis on and the startup cell will turn off. At this stage, it willenter the startup phase (soft start) with switchingcycles. After the Start Up Phase, the fault condition ischecked. If the fault condition persists, the IC will go toauto restart mode again. If, otherwise, the fault isremoved, normal operation is resumed.

    3.7.3.1 Auto Restart mode with extendedblanking time

    Figure 25 Auto Restart Mode

    In case of Overload or Open Loop, the FB exceeds4.0V which will be observed by comparator C4. Then

    the internal blanking counter starts to count. When itreaches 20ms, the switch S1 is released. Then theclamped voltage 0.9V at VBAcan increase. When thereis no external capacitor CBK connected, the VBA willreach 4.0V immediately. When both the input signals at

    AND gate G5 is positive, the Auto Restart Mode will beactivated after the extra spike blanking time of 30us iselapsed. However, when an extra blanking time isneeded, it can be achieved by adding an externalcapacitor, CBK. A constant current source of IBKwill startto charge the capacitor CBKfrom 0.9V to 4.0V after theswitch S1 is released. The charging time from 0.9V to4.0V are the extendable blanking time. If CBKis 0.22uF

    and IBKis 13uA, the extendable blanking time is around52ms and the total blanking time is 72ms. In combiningthe FB and blanking time, there is a blanking windowgenerated which prevents the system to enter AutoRestart Mode due to large load jumps.

    C3

    4.0V

    C4

    4.0V

    &

    G5

    0.9V

    S1

    1

    G2

    Control Unit

    Auto

    Restart

    Mode

    5.0VBA

    FB

    CBK

    20ms

    BlankingTime

    SpikeBlanking

    30us

    # IBK

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    C120.5V

    Spike

    Blanking

    30us

    &

    G1

    Thermal Shutdown

    Tj>140C

    Auto Restart

    mode

    VCC

    C4

    4.0V

    Voltage

    Reference

    Control Unit

    Auto Restart

    Mode Reset

    VVCC< 10.5V

    FB

    C2120us

    Blanking

    TimeVCC

    25.5V

    softs_period

    BAAuto-restartEnable

    Signal

    TAE

    C98us

    Blanking

    Time

    0.3V

    Stop

    gate

    drive

    1ms

    counterUVLO

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    3.7.3.2 Auto Restart without extended blankingtime

    Figure 26 Auto Restart mode

    There are 2 modes of VCC overvoltage protection; oneis during soft start and the other is at all conditions.

    The first one is VVCC voltage is > 20.5V and FB is > 4.0Vand during soft_start period and the IC enters AutoRestart Mode. The VCC voltage is observed bycomparator C1 and C4. The fault conditions are to

    detect the abnormal operating during start up such asopen loop during light load start up, etc. The logic caneliminate the possible of entering Auto Restart mode ifthere is a small voltage overshoots of VVCC duringnormal operating.

    The 2nd one is VVCC>25.5V and last for 120us and theIC enters Auto Restart Mode. This 25.5V Vcc OVPprotection is inactivated during burst mode.

    The Thermal Shutdown block monitors the junctiontemperature of the IC. After detecting a junctiontemperature higher than 130C, the Auto Restart Modeis entered.

    In case the pre-defined auto-restart features are not

    sufficient, there is a customer defined external Auto-restart Enable feature. This function can be triggeredby pulling down the BA pin to < 0.33V. It can simply add

    a trigger signal to the base of the externally addedtransistor, TAE at the BA pin. When the function isenabled, the gate drive switching will be stopped and

    then the IC will enter auto-restart mode if the signalpersists. To ensure this auto-restart function will not bemis-triggered during start up, a 1ms delay time isimplemented to blank the unstable signal.

    VCC undervoltage is the Vcc voltage drop below Vccturn off threshold. Then the IC will turn off and the startup cell will turn on automatically. And this leads to AutoRestart Mode.

    Short Optocoupler also leads to VCC undervoltage asthere is no self supply after activating the internalreference and bias.

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    4 Electrical Characteristics

    Note: All voltages are measured with respect to ground (Pin 5). The voltage levels are valid if other ratings arenot violated.

    4.1 Absolute Maximum Ratings

    Parameter Symbol Limit Values Unit Remarks

    min. max.

    Switching drain current, pulse width tplimited by Tj=150C

    Is - 9.95 A

    Pulse drain current, pulse width tplimitedby Tj=150C

    ID_Puls - 15.75 A

    Avalanche energy, repetitive tARlimited bymax. Tj=150C

    1)

    1) Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f

    EAR - 0.47 mJ

    Avalanche current, repetitive tARlimited bymax. Tj=150C

    1)IAR - 2.5 A

    VCC Supply Voltage VVCC -0.3 27 V

    FB Voltage VFB -0.3 5.5 VBA Voltage VBA -0.3 5.5 V

    CS Voltage VCS -0.3 5.5 V

    Junction Temperature Tj -40 150 C Controller & CoolMOS

    Storage Temperature TS -55 150 C

    Thermal ResistanceJunction -Ambient

    RthJA - 90 K/W

    Soldering temperature, wavesolderingonly allowed at leads

    Tsold - 260 C 1.6mm (0.063in.) fromcase for 10s

    ESD Capability (incl. Drain Pin) VESD

    - 2 kV Human body model2)

    2) According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kseries resistor)

    Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destructionof the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 4(VCC) is discharged before assembling the application circuit.Ta=25C unless otherwise specified.

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    4.2 Operating Range

    Note: Within the operating range the IC operates as described in the functional description.

    Parameter Symbol Limit Values Unit Remarks

    min. max.

    VCC Supply Voltage VVCC VVCCoff 25 V Max value limited due to Vcc OVP

    Junction Temperature ofController

    TjCon -25 130 C Max value limited due to thermalshut down of controller

    Junction Temperature ofCoolMOS

    TjCoolMOS -25 150 C

    4.3 Characteristics

    4.3.1 Supply Section

    Note: The electrical characteristics involve the spread of values within the specified supply voltage and junctiontemperature range TJfrom 25 C to 125 C. Typical values represent the median values, which arerelated to 25C. If not otherwise stated, a supply voltage of VCC= 18 V is assumed.

    Parameter Symbol Limit Values Unit Test Condition

    min. typ. max.

    Start Up Current IVCCstart - 150 250 A VVCC =17V

    VCC Charge Current IVCCcharge1 - - 5.0 mA VVCC = 0V

    IVCCcharge2 0.55 0.9 1.60 mA VVCC = 1V

    IVCCcharge3 - 0.7 - mA VVCC =17V

    Leakage Current ofStart Up Cell and CoolMOS

    IStartLeak - 0.2 50 A VDrain = 450Vat Tj=100C

    Supply Current withInactive Gate

    IVCCsup1 - 1.5 2.5 mA

    Supply Current with Active Gate IVCCsup2 - 3.8 4.2 mA IFB= 0A

    Supply Current inAuto Restart Mode with Inactive

    Gate

    IVCCrestart - 250 - A IFB= 0A

    Supply Current in Active BurstMode with Inactive Gate

    IVCCburst1 - 450 950 A VFB= 2.5V

    IVCCburst2 - 450 950 A VVCC = 11.5V,VFB= 2.5V

    VCC Turn-On ThresholdVCC Turn-Off ThresholdVCC Turn-On/Off Hysteresis

    VVCConVVCCoffVVCChys

    17.09.8-

    18.010.57.5

    19.011.2-

    VVV

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    Version 2.3 21 19 Nov 2012

    CoolSET-F3R

    ICE3BR0665J

    Electrical Characteristics

    4.3.2 Internal Voltage Reference

    Parameter Symbol Limit Values Unit Test Conditionmin. typ. max.

    Trimmed Reference Voltage VREF 4.90 5.00 5.10 V measured at pin FBIFB= 0

    4.3.3 PWM Section

    Parameter Symbol Limit Values Unit Test Condition

    min. typ. max.

    Fixed Oscillator Frequency fOSC1 56.5 65.0 73.5 kHz

    fOSC2 59.8 65.0 70.2 kHz Tj = 25C

    Frequency Jittering Range fjitter - 2.6 - kHz Tj = 25C

    Frequency Jittering period Tjitter - 4.0 - ms Tj = 25C

    Max. Duty Cycle Dmax 0.70 0.75 0.80

    Min. Duty Cycle Dmin 0 - - VFB< 0.3V

    PWM-OP Gain AV 3.1 3.3 3.5

    Voltage Ramp Offset VOffset-Ramp - 0.67 - V

    VFBOperating Range Min Level VFBmin - 0.5 - V

    VFBOperating Range Max level VFBmax - - 4.3 V CS=1V, limited byComparator C41)

    1) The parameter is not subjected to production test - verified by design/characterization

    FB Pull-Up Resistor RFB 9 15.4 22 k

    4.3.4 Soft Start time

    Parameter Symbol Limit Values Unit Test Condition

    min. typ. max.

    Soft Start time tSS - 20.0 - ms

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    CoolSET-F3R

    ICE3BR0665J

    Electrical Characteristics

    Version 2.3 23 19 Nov 2012

    4.3.6 Current Limiting

    Parameter Symbol Limit Values Unit Test Conditionmin. typ. max.

    Peak Current Limitation(incl. Propagation Delay)

    Vcsth 0.96 1.03 1.10 V dVsense / dt = 0.6V/s(see Figure 20)

    Peak Current Limitation duringActive Burst Mode

    VCS2 0.29 0.34 0.38 V

    Leading Edge Blanking tLEB - 220 - ns

    CS Input Bias Current ICSbias -1.5 -0.2 - A VCS =0V

    4.3.7 CoolMOSSection

    Parameter Symbol Limit Values Unit Test Condition

    min. typ. max.

    Drain Source Breakdown Voltage V(BR)DSS 650 - - V Tj= 110CRefer to Figure 30 forother V(BR)DSSindifferent Tj

    Drain Source On-Resistance RDSon --

    0.651.37

    0.751.58

    Tj= 25CTj=125C

    1)

    1) The parameter is not subjected to production test - verified by design/characterization

    at ID= 2.5A

    Effective output capacitance, energyrelated

    Co(er) - 26 - pF VDS= 0V to 480V1)

    Rise Time trise - 302)

    2) Measured in a Typical Flyback Converter Application

    - ns

    Fall Time tfall - 302) - ns

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    CoolSET-F3R

    ICE3BR0665J

    Typical CoolMOSPerformance Characteristic

    Version 2.3 24 19 Nov 2012

    5 Typical CoolMOSPerformance Characteristic

    Safe Operating Area for ICE3A(B)R0665J

    ID= f ( VDS)

    parameter : D = 0, TC= 25deg.C

    0.0001

    0.001

    0.01

    0.1

    1

    10

    100

    1 10 100 1000

    VDS[V]

    ID[

    A]

    DC

    tp = 1000ms

    tp = 1ms tp = 10ms

    tp = 100ms

    tp = 0.1ms

    tp = 0.01ms

    Figure 27 Safe Operating area (SOA) curve for ICE3BR0665J

    SOA temperature derating coefficient curve

    ( package dissipation ) for F3 & F2 CoolSET

    0

    20

    40

    60

    80

    100

    120

    0 20 40 60 80 100 120 140

    Ambient/Case temperature Ta/Tc [deg.C]

    Ta : DIP, Tc : TO220

    SOAtemperaturederatingcoefficient[%]

    Figure 28 SOA temperature derating coefficient curve

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    Allowable Power Dissipation for F3 CoolSET in DIP-8 package

    0.0

    0.2

    0.4

    0.6

    0.8

    1.0

    1.2

    1.4

    1.6

    0 20 40 60 80 100 120 140

    Ambient temperature, Ta[deg.C]

    AllowablePowerDissipation,

    Ptot[W]

    CoolSET-F3R

    ICE3BR0665J

    Typical CoolMOSPerformance Characteristic

    Version 2.3 25 19 Nov 2012

    Figure 29 Power dissipation; Ptot=f(Ta)

    540

    580

    620

    660

    700

    -60 -20 20 60 100 140 180Tj[C]

    V

    BR(DSS)[V]

    Figure 30 Drain-source breakdown voltage; VBR(DSS)=f(Tj)

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    CoolSET-F3R

    ICE3BR0665J

    Input Power Curve

    Version 2.3 26 19 Nov 2012

    6 Input Power Curve

    Two input power curves giving the typical input power versus ambient temperature are showed below;Vin=85Vac~265Vac (Figure 31) and Vin=230Vac+/-15% (Figure 32). The curves are derived based on a typicaldiscontinuous mode flyback model which considers either 50% maximum duty ratio or 100V maximum secondaryto primary reflected voltage (higher priority). The calculation is based on no copper area as heatsink for the device.The input power already includes the power loss at input common mode choke, bridge rectifier and theCoolMOS.The device saturation current (ID_Puls@ Tj=125C) is also considered.

    To estimate the output power of the device, it is simply multiplying the input power at a particular operating ambienttemperature with the estimated efficiency for the application. For example, a wide range input voltage (Figure 31),operating temperature is 50C, estimated efficiency is 85%, then the estimated output power is 42W (49W * 85%).

    Ambient Temperature [C]

    Inputpower(85~265Vac)[

    W]

    PI-001-ICE3BR0665J_85Vac

    0

    6

    12

    18

    24

    30

    36

    42

    48

    54

    60

    0 10 20 30 40 50 60 70 80 90 100 110 120 130

    Figure 31 Input power curve Vin=85~265Vac; Pin=f(Ta)

    Ambient Temperature [C]

    Inputpower(230Vac

    )[W]

    PI-002-ICE3BR0665J_

    230Vac

    0

    10

    20

    30

    40

    50

    60

    70

    80

    90

    100

    0 10 20 30 40 50 60 70 80 90 100 110 120 130

    Figure 32 Input power curve Vin=230Vac+/-15%; Pin=f(Ta)

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    CoolSET-F3R

    ICE3BR0665J

    Outline Dimension

    Version 2.3 27 19 Nov 2012

    7 Outline Dimension

    PG-DIP-8

    (Plastic Dual In-Line Outline)

    Figure 33 PG-DIP-8 (Pb-free lead plating Plastic Dual-in-Line Outline)

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    CoolSET-F3R

    ICE3BR0665J

    Marking

    Version 2.3 28 19 Nov 2012

    8 Marking

    Marking

    Figure 34 Marking for ICE3BR0665J

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    CoolSET-F3R

    ICE3BR0665J

    Schematic for recommended PCB layout

    Version 2.3 29 19 Nov 2012

    9 Schematic for recommended PCB layout

    C11

    bulk cap

    R11

    D11

    C12

    IC12

    R12

    C13

    C16

    C15

    C14

    D13R14

    R23 R22

    IC21

    C23R24

    C22

    R21

    R25

    GND

    Vo

    D21

    C21

    F3 CoolSET schematic for recommended PCB layout

    R13

    Z11

    TR1

    N

    L

    BR1

    C2

    Y-CAP

    C3

    Y-CAP

    C1

    X-CAP

    L1

    FUSE1

    C4

    Y-CAP

    GND

    Spark Gap 3

    Spark Gap 4D11

    Spark Gap 1

    Spark Gap 2

    FB

    CS

    GND NC

    BA VCCF3

    DRAIN

    CoolSET

    IC11

    *

    Figure 35 Schematic for recommended PCB layout

    General guideline for PCB layout design using F3/F3R CoolSET(refer to Figure 35):

    1. Star Ground at bulk capacitor ground, C11:

    Star Ground means all primary DC grounds should be connected to the ground of bulk capacitor C11separately in one point. It can reduce the switching noise going into the sensitive pins of the CoolSETdeviceeffectively. The primary DC grounds include the followings.

    a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.

    b. DC ground of the current sense resistor, R12

    c. DC ground of the CoolSETdevice, GND pin of IC11; the signal grounds from C13, C14, C15 and collectorof IC12 should be connected to the GND pin of IC11 and then star connect to the bulk capacitor ground.

    d. DC ground from bridge rectifier, BR1

    e. DC ground from the bridging Y-capacitor, C4

    2. High voltage traces clearance:

    High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.

    a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm

    b. 600V traces (drain voltage of CoolSETIC11) to nearby trace: > 2.5mm

    3. Filter capacitor close to the controller ground:

    Filter capacitors, C13, C14 and C15 should be placed as close to the controller ground and the controller pinas possible so as to reduce the switching noise coupled into the controller.

    Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 35):

    1. Add spark gap

    Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulatedcharge during surge test through the sharp point of the saw-tooth plate.

    a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:

    Gap separation is around 1.5mm (no safety concern)

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    CoolSET-F3R

    ICE3BR0665J

    Schematic for recommended PCB layout

    Version 2.3 30 19 Nov 2012

    b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:

    These 2 Spark Gaps can be used when the lightning surge requirement is >6KV.

    230Vac input voltage application, the gap separation is around 5.5mm115Vac input voltage application, the gap separation is around 3mm

    2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin input

    3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:

    The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSETandreduce the abnormal behavior of the CoolSET. The diode can be a fast speed diode such as IN4148.

    The principle behind is to drain the high surge voltage from Live/Neutral to Ground without passing through thesensitive components such as the primary controller, IC11.

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