circuitos lógicos e organização de computadores capítulo 7 – flip-flops e circuitos...

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1 Circuitos Lógicos e Organização de Computadores Capítulo 7 – Flip-Flops e Circuitos Seqüenciais Ricardo Pannain [email protected] http://docentes.puc-campinas.edu.br/ ceatec/pannain/

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Circuitos Lógicos e Organização de Computadores Capítulo 7 – Flip-Flops e Circuitos Seqüenciais. Ricardo Pannain [email protected] http://docentes.puc-campinas.edu.br/ceatec/pannain/. Set. Sensor. ¤. On. Off. Memory. Alarm. element. Reset. Circuito Seqüenciais. - PowerPoint PPT Presentation

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1

Circuitos Lógicos e Organização de Computadores

Capítulo 7 – Flip-Flops e Circuitos Seqüenciais

Ricardo [email protected]

http://docentes.puc-campinas.edu.br/ceatec/pannain/

2

Exemplo - Controle de Sistema de Alarme

Memoryelement Alarm

Sensor

Reset

Set On Off

Circuito combinacional saídas dependem apenas das entradas

Cicuito seqüencial saídas dependem das entradas e do comportamento anterior do circuito

Circuito Seqüenciais

3

Elemento de memória simples

A B

A B OutputData

Load

TG1

TG2

Elemento de memória controladoReset

Set Q

Elemento de memória com portas NOR

4

Latch construído com portas NOR

Time

1

0

1

0

1

0

1

0

R

S

Qa

Qb

?

?

(c) Diagrama de Tempo

t1 t2 t3 t4 t5 t6 t7 t8 t9 t10

(a) Circuito

Qa

Qb

R

S

S R Qa Qb

0 00 11 01 1

0/11/00 11 00 0

(b) Tabela Verdade

(sem alteração)

5

Latch SR com clock (gated)

(a) Circuito

Q

Q

R

S

R

S

Clk

S R

x x 0 0 0 1 1 0

Q(t ) (sem alteração)

0 1

Clk

0 1 1 1

1 1 1

Q t 1 +

Q(t ) (sem alteração)

x

(b) Tabela Verdade

R

Clk

Q

Q

S

1 0 1 0 1 0 1 0 1 0

Time(c) Timing diagram

?

?

S Q

Q Clk

R

(d) Símbolo Gráfico

6

Latch SR Gated SR com portas NAND

S

R

Clk

Q

Q

7

Latch D Gated

Q

S

R

Clk

D (Data)

(a) Circuito

Q

Clk D 0 1 1

x 0 1

0 1

Q t 1 +

Q t

(b) Tabela Verdade

D Q

Q Clk

(c) Símbolo Gráficot 1 t 2 t 3 t 4

Time

Clk

D

Q

(d) Diagrama de Tempo

8

Setup and hold times

t sut h

Clk

D

Q

Setup time tempo mínimo que D deve estar estável antes da descida do clock

Hold time temp mínimo que D deve ser mantido estável após a descida do clock

Valores típos (CMOS): tsu = 3ns e th = 2ns

9

Flip-Flop D Master-slave

D Q

Q

Master Slave

D

Clock

Q

Q

D Q

Q

Q m Q s

(a) Circuito

Clk Clk

D

Clock

Q m

Q Q s =

(b) Diagrama de tempo

D Q

Q

(c) Símbolo Gráfico

CLK = 1 master armazenae slave não mudaCLK = 0 master não mudae slave armazena

Sensível à borda de descida

10

Flip-Flop D sensível à borda de subida

D Q

Q

(b) Símbolo Gráfico

Clock

D

Clock

P4

P3

P1

P2

5

6

1

2

3

(a) Circuito

Q

Q

4 Clk = 0 P1 = P2 = 1

P3 = DP4 = D

Clk =1 P3 e P4 são transmitidos através de 2 e 3

P1 = D e P2 = D Q = D e Q = D

Obs - P4 e P3 DEVEM ESTAR ESTÁVEIS QUANDO CLK MUDA PARA 1

11

Comparação de Flip-Flops D sensíveis a nivel e sensíveis a borda

D Q

Q

D Q

Q

D Q

Q

D

Clock Q a

Q b

Q c

Q c

Q b

Q a

(a) Circuito

Clk

D

Q a

Q b

Q c

(b) Diagrama de Tempo

Clock

12

Flip-Flop Master-slave tipo D com Clear e Preset

D Q

Q

(b) Símbolo Gráfico

Clear

Preset

Q

Q

D

Clock

(a) Circuito

Preset

Clear

13

Flip-Flop D sensível à borda de subida com Clear e Preset

D

Clock

(a) Circuito

Q

Q

Clear

Preset

Preset

Clear

(b) Símbolo Gráfico

D Q

Q

14

Flip-Flop D com reset síncrono

D

Clock Q

QClear

D Q

Q

15

Flip-Flop tipo T (toogle)

D Q

Q

Q

Q T

Clock

(a) Circuito

T 0 1

Q t 1 +

Q t

Q t

(b) Tabela Verdade

T Q

Q

(c) Símbolo Gráfico

Clock

T

Q

(d) Diagrama de tempo

16

Flip-Flop JK

D Q

Q

Q

Q

J

Clock

(a) Circuito

K

J Q

Q

(c) Símbolo Gráfico

K

K

01

Q t 1+ Q t

0

(b) Tabela Verdade

J

00

0 111 Q t 1

D = J Q + K Q

J e K entradasDe controle

FFs SR e T juntos

17

Registrador de deslocamento com entrada e saída serial

t 0 t 1 t 2 t 3 t 4 t 5 t 6 t 7

1 0 1 1 1 0 0 0

0 1 0 1 1 1 0 0

0 0 1 0 1 1 1 0

0 0 0 1 0 1 1 1

0 0 0 0 1 0 1 1

Q 1 Q 2 Q 3 Q 4 Out = In

(b) Exemplo de uma seqüência

D Q

Q Clock

D Q

Q

D Q

Q

D Q

Q

In Out

(a) Circuito

Q 1 Q 2 Q 3 Q 4

Registrador é um conjunto de n Flip-Flops

FFs master-slave ou sensível à borda.

Porque não sensível a nível ?

18

Registrador de deslocamento com entrada paralela e serial e saída paralela

Q3 Q2 Q1 Q0

ClockParallel input

Parallel output

Shift/LoadSerialinput

D Q

Q

D Q

Q

D Q

Q

D Q

Q

19

ContadoresContador de 3 bits up-counter

T Q

Q Clock

T Q

Q

T Q

Q

1

Q 0 Q 1 Q 2

(a) Circuito Clock

Q 0

Q 1

Q 2

Count 0 1 2 3 4 5 6 7 0

(b) Diagrama de tempo

20

Contador de 3 bits down-counter

Clock

(a) Circuit

T Q

Q

T Q

Q

T Q

Q

1

Q 0 Q 1 Q 2

Clock

Q 0

Q 1

Q 2

Count 0 7 6 5 4 3 2 1 0

(b) Timing diagram

21

Derivação de contador síncrono up-counter

0 0 1 1

0 1 0 1

0 1 2 3

0 0 1

0 1 0

4 5 6

1 1 7

0 0 0 0 1 1 1 1

Clock cycle

0 0 8 0

Q 2 Q1 Q0 Q 1 muda

Q 2 mudaT0 = 1T1 = Q0T2 = Q0 Q1T3 = Q0 Q1 Q2Tn = Q0 Q1 ... Qn

22

Contador síncrocno de quatro-bits up-counter

Clock

Q 0

Q 1

Q 2

Count 0 1 2 3 5 9 12 14 0

(b) Diagrama de tempo

Q 3

4 6 8 7 10 11 13 15 1

T Q

Q Clock

T Q

Q

T Q

Q

1 Q 0 Q 1 Q 2

(a) Circuito

T Q

Q Q 3

23

Inclusão de sinais de enable e clear

T Q

Q Clock

T Q

Q

Enable

Clear

T Q

Q

T Q

Q

24

Contador de 4 bits com FF D

Clock

Enable D Q

Q

D Q

Q

D Q

Q

D Q

Q

Q0

Q1

Q2

Q3

Outputcarry

25

Contador com entrada paralela

Enable D Q Q

Q 0

D Q Q

Q 1

D Q Q

Q 2

D Q Q

Q 3

D 0

D 1

D 2

D 3

LoadClock

Outputcarry

0 1

0 1

0 1

0 1

26

Contador modulo-6 com reset síncrono

0 1 2 3 4 5 0 1

Clock

Count

Q 0

Q 1

Q 2

(b) Diagrama de tempo

EnableQ 0 Q 1 Q 2

D 0 D 1 D 2 LoadClock

1 0 0 0

Clock

(a) Circuito

27

Contador modulo-6 com reset síncrono

Clock

Q 0

Q 1

Q 2

Count

(b) Diagrama de tempo

0 1 2 3 4 5 0 1 2

(a) Circuito

T Q

Q Clock

T Q

Q

T Q

Q

1 Q 0 Q 1 Q 2

28

Contador BCD de 2 dígitos

EnableQ0Q1Q2

D0D1D2

LoadClock

1000

Clock

Q30 D3

EnableQ0Q1Q2

D0D1D2

LoadClock

000

Q30 D3

BCD0

BCD1

Clear

29

Contador em Anel

1000, 0100, 0010, 0001

D Q

Q

Clock

D Q

Q

D Q

Q

Start

Q 0 Q 1 Q n 1 ”

Clock

Q 0

Start

Two-bit up-counter

w 0 En

y 0

w 1

y 1 y 2 y 3

1

Q 1 Q 2 Q 3

2-to-4 decoder

Q 1 Q 0

(a) An n -bit ring counter

Clock

Clear

(b) A four-bit ring counter

30

Contador Johnson

D Q

Q

Clock

D Q

Q

D Q

Q

Q 0 Q 1 Q n 1 –

Reset

31

Inatalação de um FF D de um package

LIBRARY ieee ;USE ieee.std_logic_1164.all ;LIBRARY altera ; USE altera.maxplus2.all ;

ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ;

Resetn, Presetn : IN STD_LOGIC ; Q : OUT STD_LOGIC ) ;

END flipflop ;

ARCHITECTURE Structure OF flipflop IS BEGIN

dff_instance: dff PORT MAP ( D, Clock, Resetn, Presetn, Q ) ; END Structure ;

32

Memória

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY implied ISPORT ( A, B : IN STD_LOGIC ;

AeqB : OUT STD_LOGIC ) ;END implied ;

ARCHITECTURE Behavior OF implied ISBEGIN

PROCESS ( A, B )BEGIN

IF A = B THENAeqB <= '1' ;

END IF ;END PROCESS ;

END Behavior ;

33

Codigo para um latch D gated

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY latch IS PORT ( D, Clk : IN STD_LOGIC ;

Q : OUT STD_LOGIC) ; END latch ;

ARCHITECTURE Behavior OF latch IS BEGIN

PROCESS ( D, Clk ) BEGIN

IF Clk = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

34

Código para um FF D

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESS ( Clock ) BEGIN

IF Clock'EVENT AND Clock = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

35

Código para um FF D usando WAIT UNTIL

LIBRARY ieee; USE ieee.std_logic_1164.all;

ENTITY flipflop IS PORT ( D, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC ) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;Q <= D ;

END PROCESS ; END Behavior ;

36

FF D com reset assíncrono

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESS ( Resetn, Clock ) BEGIN

IF Resetn = '0' THEN Q <= '0' ;

ELSIF Clock'EVENT AND Clock = '1' THEN Q <= D ;

END IF ; END PROCESS ;

END Behavior ;

37

LIBRARY ieee ; USE ieee.std_logic_1164.all ;

ENTITY flipflop IS PORT ( D, Resetn, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC) ; END flipflop ;

ARCHITECTURE Behavior OF flipflop IS BEGIN

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF Resetn = '0' THEN

Q <= '0' ; ELSE

Q <= D ; END IF ;

END PROCESS ;END Behavior ;

FF D com reset síncrono

38

Instanciação do módulo lpm_shiftreg

LIBRARY ieee ; USE ieee.std_logic_1164.all ; LIBRARY lpm ;USE lpm.lpm_components.all ;

ENTITY shift ISPORT ( Clock : IN STD_LOGIC ;

Reset : IN STD_LOGIC ;Shiftin, Load : IN STD_LOGIC ;R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END shift ;

ARCHITECTURE Structure OF shift ISBEGIN

instance: lpm_shiftregGENERIC MAP (LPM_WIDTH => 4, LPM_DIRECTION => "RIGHT")PORT MAP (data => R, clock => Clock, aclr => Reset,

load => Load, shiftin => Shiftin, q => Q ) ;END Structure ;

39

Código um registrador de 8 bits com clear assíncrono

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY reg8 ISPORT ( D : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;

Resetn, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;

END reg8 ;

ARCHITECTURE Behavior OF reg8 ISBEGIN

PROCESS ( Resetn, Clock )BEGIN

IF Resetn = '0' THENQ <= "00000000" ;

ELSIF Clock'EVENT AND Clock = '1' THENQ <= D ;

END IF ;END PROCESS ;

END Behavior ;

40

Código um registrador de n-bit com clear assíncrono

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY regn ISGENERIC ( N : INTEGER := 16 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Resetn, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END regn ;

ARCHITECTURE Behavior OF regn ISBEGIN

PROCESS ( Resetn, Clock )BEGIN

IF Resetn = '0' THENQ <= (OTHERS => '0') ;

ELSIF Clock'EVENT AND Clock = '1' THENQ <= D ;

END IF ;END PROCESS ;

END Behavior ;

41

Código para um FF D com um multiplexador 2-para-1 na entrada D

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY muxdff ISPORT ( D0, D1, Sel, Clock : IN STD_LOGIC ;

Q : OUT STD_LOGIC ) ;END muxdff ;

ARCHITECTURE Behavior OF muxdff ISBEGIN

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF Sel = '0' THEN

Q <= D0 ;ELSE

Q <= D1 ;END IF ;

END PROCESS ;END Behavior ;

42

Código hierárquico para um shift-register de 4 bits

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY shift4 ISPORT ( R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

L, w, Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END shift4 ;

ARCHITECTURE Structure OF shift4 ISCOMPONENT muxdff

PORT ( D0, D1, Sel, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC ) ;

END COMPONENT ;BEGIN

Stage3: muxdff PORT MAP ( w, R(3), L, Clock, Q(3) ) ;Stage2: muxdff PORT MAP ( Q(3), R(2), L, Clock, Q(2) ) ;Stage1: muxdff PORT MAP ( Q(2), R(1), L, Clock, Q(1) ) ;Stage0: muxdff PORT MAP ( Q(1), R(0), L, Clock, Q(0) ) ;

END Structure ;

43

Alternativa para o shift register

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY shift4 IS

PORT ( R : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;Clock : IN STD_LOGIC ;L, w : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END shift4 ;

ARCHITECTURE Behavior OF shift4 ISBEGIN

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF L = '1' THEN

Q <= R ;ELSE

Q(0) <= Q(1) ;Q(1) <= Q(2); Q(2) <= Q(3) ; Q(3) <= w ;

END IF ;END PROCESS ;

END Behavior ;

44

Contador up-counter quatro-bits

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY upcount IS

PORT ( Clock, Resetn, E : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)) ;

END upcount ;

ARCHITECTURE Behavior OF upcount ISSIGNAL Count : STD_LOGIC_VECTOR (3 DOWNTO 0) ;

BEGINPROCESS ( Clock, Resetn )BEGIN

IF Resetn = '0' THENCount <= "0000" ;

ELSIF (Clock'EVENT AND Clock = '1') THENIF E = '1' THEN

Count <= Count + 1 ;ELSE

Count <= Count ;END IF ;

END IF ;END PROCESS ;Q <= Count ;

END Behavior ;

45

Contador de 4 bits com carga paralela usando sinais INTEGER

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY upcount ISPORT ( R : IN INTEGER RANGE 0 TO 15 ;

Clock, Resetn, L : IN STD_LOGIC ;Q : BUFFER INTEGER RANGE 0 TO 15 ) ;

END upcount ;

ARCHITECTURE Behavior OF upcount ISBEGIN

PROCESS ( Clock, Resetn )BEGIN

IF Resetn = '0' THENQ <= 0 ;

ELSIF (Clock'EVENT AND Clock = '1') THENIF L = '1' THEN

Q <= R ;ELSE

Q <= Q + 1 ;END IF;

END IF;END PROCESS;

END Behavior;

46

Contador down-counter

LIBRARY ieee ;USE ieee.std_logic_1164.all ;ENTITY downcnt IS

GENERIC ( modulus : INTEGER := 8 ) ;PORT ( Clock, L, E : IN STD_LOGIC ;

Q : OUT INTEGER RANGE 0 TO modulus-1 ) ;END downcnt ;

ARCHITECTURE Behavior OF downcnt ISSIGNAL Count : INTEGER RANGE 0 TO modulus-1 ;

BEGINPROCESSBEGIN

WAIT UNTIL (Clock'EVENT AND Clock = '1') ;IF E = '1' THEN

IF L = '1' THENCount <= modulus-1 ;

ELSECount <= Count-1 ;

END IF ;END IF ;

END PROCESS;Q <= Count ;

END Behavior ;

47

Sistema digital com k registradores

R 1 in Rkin

Bus

Clock

R 1 out R 2 in R 2 out Rkout

Control circuit Function

R 1 R 2 Rk

Data

Extern

48

Conexão dos registradoes ao barramento

D Q

Q

Clock

D Q

Q

R 1 i n

R 1 o u t

D Q

Q

D Q

Q

R 2 i n

R 2 o u t

Bus

R 1 R 2

49

Circuito de controle com um shift-register

D Q

Q Clock

D Q

Q

D Q

Q

w

R 2 out R 3 in

Reset

R 1 out R 2 in R 3 out R 1 in

50

Circuito de controle modificado

D Q

Q Clock

D Q

Q

D Q

Q

w

R 2 out R 3 in R 1 out R 2 in R 3 out R 1 in

P

Reset

51

Cicuito de controle com FF sem preset

D Q

Q Clock

D Q

Q

D Q

Q

w

R 2 out R 3 in R 1 out R 2 in R 3 out R 1 in

Reset

52

Usando multiplexadores para implementação de um barramento

Data

R 1 in

Multiplexers

R 2 in Rkin

Bus

Clock

S j 1 –

S 0

R 1 R 2 Rk

53

Código para registrador de n-bits com enable

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY regn ISGENERIC ( N : INTEGER := 8 ) ;PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Rin, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END regn ;

ARCHITECTURE Behavior OF regn ISBEGIN

PROCESSBEGIN

WAIT UNTIL Clock'EVENT AND Clock = '1' ;IF Rin = '1' THEN

Q <= R ;END IF ;

END PROCESS ;END Behavior ;

54

Código para buffer tri-sate n-bits

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY trin ISGENERIC ( N : INTEGER := 8 ) ;PORT ( X : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

E : IN STD_LOGIC ;F : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END trin ;

ARCHITECTURE Behavior OF trin ISBEGIN

F <= (OTHERS => 'Z') WHEN E = '0' ELSE X ;END Behavior ;

55

Código para controlador com for the shift-register

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY shiftr IS -- left-to-right shift register with async resetGENERIC ( K : INTEGER := 4 ) ;PORT ( Resetn, Clock, w : IN STD_LOGIC ;

Q : BUFFER STD_LOGIC_VECTOR(1 TO K) ) ;END shiftr ;

ARCHITECTURE Behavior OF shiftr ISBEGIN

PROCESS ( Resetn, Clock )BEGIN

IF Resetn = '0' THENQ <= (OTHERS => '0') ;

ELSIF Clock'EVENT AND Clock = '1' THENGenbits: FOR i IN K DOWNTO 2 LOOP

Q(i) <= Q(i-1) ;END LOOP ;Q(1) <= w ;

END IF ;END PROCESS ;

END Behavior ;

56

Declaração de package e component

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

PACKAGE components ISCOMPONENT regn -- register

GENERIC ( N : INTEGER := 8 ) ;PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Rin, Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END COMPONENT ;

COMPONENT shiftr -- left-to-right shift register with async resetGENERIC ( K : INTEGER := 4 ) ;PORT ( Resetn, Clock, w : IN STD_LOGIC ;

Q : BUFFER STD_LOGIC_VECTOR(1 TO K) ) ;END component ;

COMPONENT trin -- tri-state buffersGENERIC ( N : INTEGER := 8 ) ;PORT ( X : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

E : IN STD_LOGIC ;F : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END COMPONENT ;END components ;

57

Sistema digital com bus

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.components.all ;

ENTITY swap ISPORT ( Data : IN STD_LOGIC_VECTOR(7

DOWNTO 0) ;Resetn, w : IN STD_LOGIC ;Clock, Extern : IN STD_LOGIC ;RinExt : IN STD_LOGIC_VECTOR(1 TO 3) ;BusWires : INOUT STD_LOGIC_VECTOR(7

DOWNTO 0) ) ;END swap ;

58

ARCHITECTURE Behavior OF swap ISSIGNAL Rin, Rout, Q : STD_LOGIC_VECTOR(1 TO 3) ;SIGNAL R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;

BEGINcontrol: shiftr GENERIC MAP ( K => 3 )

PORT MAP ( Resetn, Clock, w, Q ) ;Rin(1) <= RinExt(1) OR Q(3) ;Rin(2) <= RinExt(2) OR Q(2) ;Rin(3) <= RinExt(3) OR Q(1) ;Rout(1) <= Q(2) ; Rout(2) <= Q(1) ; Rout(3) <= Q(3) ;

tri_ext: trin PORT MAP ( Data, Extern, BusWires ) ;reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;tri1: trin PORT MAP ( R1, Rout(1), BusWires ) ;tri2: trin PORT MAP ( R2, Rout(2), BusWires ) ;tri3: trin PORT MAP ( R3, Rout(3), BusWires ) ;

END Behavior ;

Sistema digital com bus - continuação

59

Usando multiplexadores para implementar um bus

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.components.all ;

ENTITY swapmux ISPORT ( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;

Resetn, w : IN STD_LOGIC ;Clock : IN STD_LOGIC ;RinExt : IN STD_LOGIC_VECTOR(1 TO 3) ;BusWires : BUFFER STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;

END swapmux ;

ARCHITECTURE Behavior OF swapmux ISSIGNAL Rin, Q : STD_LOGIC_VECTOR(1 TO 3) ;SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0) ;SIGNAL R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;

BEGINcontrol: shiftr GENERIC MAP ( K => 3 )

PORT MAP ( Resetn, Clock, w, Q ) ;

… con’t

60

Rin(1) <= RinExt(1) OR Q(3) ;Rin(2) <= RinExt(2) OR Q(2) ;Rin(3) <= RinExt(3) OR Q(1) ;reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;encoder:WITH Q SELECT

S <= "00" WHEN "000","10" WHEN "100","01" WHEN "010","11" WHEN OTHERS ;

muxes: --eight 4-to-1 multiplexersWITH S SELECT

BusWires <= Data WHEN "00",R1 WHEN "01",R2 WHEN "10",R3 WHEN OTHERS ;

END Behavior ;

Usando multiplexadores para implementar um bus - continuação

61

Código simplificado para descrever um barramento

(ENTITY declaration not shown)

ARCHITECTURE Behavior OF swapmux ISSIGNAL Rin, Q : STD_LOGIC_VECTOR(1 TO 3) ;SIGNAL R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;

BEGINcontrol: shiftr GENERIC MAP ( K => 3 )

PORT MAP ( Resetn, Clock, w, Q ) ;Rin(1) <= RinExt(1) OR Q(3) ;Rin(2) <= RinExt(2) OR Q(2) ;Rin(3) <= RinExt(3) OR Q(1) ;

reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;

muxes:WITH Q SELECT

BusWires <= Data WHEN "000",R2 WHEN "100",R1 WHEN "010",R3 WHEN OTHERS ;

END Behavior ;

62

Sistema digital implementa um processador simples

R 3 i n

Bus

Clock

R 0 i n R 0 o u t R 3 o u t

Control circuit Function

G

R 0 R3 A

AddSub

A i n G i n G o u t

Extern

Data

w

Done

B

63

Operacões executadas pelo processador

64

Circuito de controle do porcessador

Reset Up-counter

Clear

w 0 En

y 0

w 1

y 1 y 2 y 3

1

T 1 T 2 T 3

2-to-4 decoder

Q 1 Q 0 Clock

T 0

65

Registrador de função e os decodificadores

Clock

X 0

w 0 En

y 0

w 1

y 1 y 2 y 3

1

X 1 X 2 X 3

2-to-4 decoder

Function Register

Y 0

w 0 En

y 0

w 1

y 1 y 2 y 3

1

Y 1 Y 2 Y 3

2-to-4 decoder

I 0

En

y 0 y 1 y 2 y 3

1

I 1 I 2 I 3

2-to-4 decoder

FRin

f 1 f 0 Rx1 Rx0 Ry1 Ry0

w 0 w 1

Function

66

Valores dos sinais de controle para cada operação/time step

67

Código para two-bit up-counter reset assíncrono

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;ENTITY upcount IS

PORT ( Clear, Clock : IN STD_LOGIC ;Q : BUFFER STD_LOGIC_VECTOR(1 DOWNTO 0) ) ;

END upcount ;

ARCHITECTURE Behavior OF upcount ISBEGIN

upcount: PROCESS ( Clock )BEGIN

IF (Clock'EVENT AND Clock = '1') THENIF Clear = '1' THEN

Q <= "00" ;ELSE

Q <= Q + '1' ;END IF ;

END IF;END PROCESS;

END Behavior ;

68

Código para o processador

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_signed.all ;USE work.subccts.all ;

ENTITY proc ISPORT ( Data : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;

Reset, w : IN STD_LOGIC ;Clock : IN STD_LOGIC ;F, Rx, Ry : IN STD_LOGIC_VECTOR(1 DOWNTO 0) ;Done : BUFFER STD_LOGIC ;BusWires : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ;

END proc ;

ARCHITECTURE Behavior OF proc ISSIGNAL Rin, Rout : STD_LOGIC_VECTOR(0 TO 3) ;SIGNAL Clear, High, AddSub : STD_LOGIC ;SIGNAL Extern, Ain, Gin, Gout, FRin : STD_LOGIC ;SIGNAL Count, Zero : STD_LOGIC_VECTOR(1 DOWNTO 0) ;SIGNAL T, I, X, Y : STD_LOGIC_VECTOR(0 TO 3) ;SIGNAL R0, R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;SIGNAL A, Sum, G : STD_LOGIC_VECTOR(7 DOWNTO 0) ;SIGNAL Func, FuncReg : STD_LOGIC_VECTOR(1 TO 6) ;

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BEGINZero <= "00" ; High <= '1' ;Clear <= Reset OR Done OR (NOT w AND T(0)) ;counter: upcount PORT MAP ( Clear, Clock, Count ) ;decT: dec2to4 PORT MAP ( Count, High, T );Func <= F & Rx & Ry ;FRin <= w AND T(0) ;functionreg: regn GENERIC MAP ( N => 6 )

PORT MAP ( Func, FRin, Clock, FuncReg ) ;decI: dec2to4 PORT MAP ( FuncReg(1 TO 2), High, I ) ;decX: dec2to4 PORT MAP ( FuncReg(3 TO 4), High, X ) ;decY: dec2to4 PORT MAP ( FuncReg(5 TO 6), High, Y ) ;

Extern <= I(0) AND T(1) ;Done <= ((I(0) OR I(1)) AND T(1)) OR ((I(2) OR I(3)) AND T(3)) ;Ain <= (I(2) OR I(3)) AND T(1) ;Gin <= (I(2) OR I(3)) AND T(2) ;Gout <= (I(2) OR I(3)) AND T(3) ;AddSub <= I(3) ;

… con’t

Código para o processador - continuação

70

RegCntl:FOR k IN 0 TO 3 GENERATE

Rin(k) <= ((I(0) OR I(1)) AND T(1) AND X(k)) OR((I(2) OR I(3)) AND T(3) AND X(k)) ;

Rout(k) <= (I(1) AND T(1) AND Y(k)) OR ((I(2) OR I(3)) AND ((T(1) AND X(k)) OR (T(2) AND Y(k)))) ;

END GENERATE RegCntl ;tri_extern: trin PORT MAP ( Data, Extern, BusWires ) ;reg0: regn PORT MAP ( BusWires, Rin(0), Clock, R0 ) ;reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;tri0: trin PORT MAP ( R0, Rout(0), BusWires ) ;tri1: trin PORT MAP ( R1, Rout(1), BusWires ) ;tri2: trin PORT MAP ( R2, Rout(2), BusWires ) ;tri3: trin PORT MAP ( R3, Rout(3), BusWires ) ;regA: regn PORT MAP ( BusWires, Ain, Clock, A ) ;alu:WITH AddSub SELECT

Sum <= A + BusWires WHEN '0',A - BusWires WHEN OTHERS ;

regG: regn PORT MAP ( Sum, Gin, Clock, G ) ;triG: trin PORT MAP ( G, Gout, BusWires ) ;

END Behavior ;

Código para o processador - continuação

71

Alternativa para o código do processador

… (ENTITY declaration not shown)ARCHITECTURE Behavior OF proc IS

SIGNAL X, Y, Rin, Rout : STD_LOGIC_VECTOR(0 TO 3) ;SIGNAL Clear, High, AddSub : STD_LOGIC ;SIGNAL Extern, Ain, Gin, Gout, FRin : STD_LOGIC ;SIGNAL Count, Zero, T, I : STD_LOGIC_VECTOR(1 DOWNTO 0) ;SIGNAL R0, R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0) ;SIGNAL A, Sum, G : STD_LOGIC_VECTOR(7 DOWNTO 0) ;SIGNAL Func, FuncReg, Sel : STD_LOGIC_VECTOR(1 TO 6) ;

BEGINZero <= "00" ; High <= '1' ;Clear <= Reset OR Done OR (NOT w AND NOT T(1) AND NOT T(0)) ;counter: upcount PORT MAP ( Clear, Clock, Count ) ;T <= Count ;Func <= F & Rx & Ry ;FRin <= w AND NOT T(1) AND NOT T(0) ;functionreg: regn GENERIC MAP ( N => 6 )

PORT MAP ( Func, FRin, Clock, FuncReg ) ;I <= FuncReg(1 TO 2) ;decX: dec2to4 PORT MAP ( FuncReg(3 TO 4), High, X ) ;decY: dec2to4 PORT MAP ( FuncReg(5 TO 6), High, Y ) ;controlsignals: PROCESS ( T, I, X, Y )BEGIN

… con’t

72

Extern <= '0' ; Done <= '0' ; Ain <= '0' ; Gin <= '0' ;Gout <= '0' ; AddSub <= '0' ; Rin <= "0000" ; Rout <= "0000" ;CASE T IS

WHEN "00" => -- no signals asserted in time step T0WHEN "01" => -- define signals asserted in time step T1

CASE I ISWHEN "00" => -- Load

Extern <= '1' ; Rin <= X ; Done <= '1' ;WHEN "01" => -- Move

Rout <= Y ; Rin <= X ; Done <= '1' ;WHEN OTHERS => -- Add, Sub

Rout <= X ; Ain <= '1' ;END CASE ;

WHEN "10" => -- define signals asserted in time step T2CASE I IS

WHEN "10" => -- AddRout <= Y ; Gin <= '1' ;

WHEN "11" => -- SubRout <= Y ; AddSub <= '1' ; Gin <= '1' ;

WHEN OTHERS => -- Load, MoveEND CASE ;

WHEN OTHERS => -- define signals asserted in time step T3CASE I IS

Alternativa para o código do processador - continuação

73

WHEN "00" => -- LoadWHEN "01" => -- MoveWHEN OTHERS => -- Add, Sub

Gout <= '1' ; Rin <= X ; Done <= '1' ;END CASE ;

END CASE ;END PROCESS ;reg0: regn PORT MAP ( BusWires, Rin(0), Clock, R0 ) ;reg1: regn PORT MAP ( BusWires, Rin(1), Clock, R1 ) ;reg2: regn PORT MAP ( BusWires, Rin(2), Clock, R2 ) ;reg3: regn PORT MAP ( BusWires, Rin(3), Clock, R3 ) ;regA: regn PORT MAP ( BusWires, Ain, Clock, A ) ;alu: WITH AddSub SELECT

Sum <= A + BusWires WHEN '0',A - BusWires WHEN OTHERS ;

regG: regn PORT MAP ( Sum, Gin, Clock, G ) ;Sel <= Rout & Gout & Extern ;WITH Sel SELECT

BusWires <= R0 WHEN "100000",R1 WHEN "010000",R2 WHEN "001000",R3 WHEN "000100",G WHEN "000010",Data WHEN OTHERS ;

END Behavior ;

Alternativa para o código do processador - continuação

74

Um circuito reaction-timer

(a) Clock divider

10-bit counterClock

c 0 c 1 c 9

DD

R L

DD

V LED

(b) LED circuit

75

D Q

Q

Two-digit BCD counter

w 0

a

w 1

b

w 2 w 3

g

w 0

a

w 1

b

w 2 w 3

g

BCD 0 BCD 1 E

Converter Converter

c 9

V DD

R

w

V DD

R L

(c) Push-button switch, LED, and 7-segment displays

Reset Clear

1 0 1

Um circuito reaction-timer

76

Código para contador BCD de dois dígitos

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;

ENTITY BCDcount ISPORT ( Clock : IN STD_LOGIC ;

Clear, E : IN STD_LOGIC ;BCD1, BCD0 : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END BCDcount ;

ARCHITECTURE Behavior OF BCDcount ISBEGIN

PROCESS ( Clock )BEGIN

IF Clock'EVENT AND Clock = '1' THENIF Clear = '1' THEN

BCD1 <= "0000" ; BCD0 <= "0000" ;… con’t

77

ELSIF E = '1' THENIF BCD0 = "1001" THEN

BCD0 <= "0000" ;IF BCD1 = "1001" THEN

BCD1 <= "0000";ELSE

BCD1 <= BCD1 + '1' ;END IF ;

ELSEBCD0 <= BCD0 + '1' ;

END IF ;END IF ;

END IF;END PROCESS;

END Behavior ;

Código para contador BCD de dois dígitos

78

Código para o reaction timer

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY reaction ISPORT ( c9, Reset : IN STD_LOGIC ;

w, Pushn : IN STD_LOGIC ;LEDn : OUT STD_LOGIC ;Digit1, Digit0 : BUFFER STD_LOGIC_VECTOR(1 TO 7) ) ;

END reaction ;

ARCHITECTURE Behavior OF reaction ISCOMPONENT BCDcount

PORT ( Clock : IN STD_LOGIC ;Clear, E : IN STD_LOGIC ;BCD1, BCD0 : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0) ) ;

END COMPONENT ;COMPONENT seg7

PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;

END COMPONENT ;SIGNAL LED : STD_LOGIC ;SIGNAL BCD1, BCD0 : STD_LOGIC_VECTOR(3 DOWNTO 0) ;

… con’t

79

Código para o reaction timer (continuação)

BEGINflipflop: PROCESSBEGIN

WAIT UNTIL c9'EVENT AND c9 = '1' ;IF Pushn = '0' THEN

LED <= '0' ;ELSIF w = '1' THEN

LED <= '1' ;END IF ;

END PROCESS ;

LEDn <= NOT LED ;counter: BCDcount PORT MAP ( c9, Reset, LED, BCD1, BCD0 ) ;seg1 : seg7 PORT MAP ( BCD1, Digit1 ) ;seg0 : seg7 PORT MAP ( BCD0, Digit0 ) ;

END Behavior ;