1. 2 memória (r-bit register) circuito combinatório d1d1 drdr trtr t1t1 x1x1 xlxl y1y1 ynyn...

2

Memória (R-bit register)

Circuito Combinatório

D1 DR TRT1

X1

XL

Y1

YN

clock reset

3

MEF

4

Para um dado vector binário BVector de N bits verificar se este vector contém M uns consecutivos: responder Sim (Yes) ou Não (No)

Exemplo: BVector = 0101011011101011;N = 16;dado M = 3 resposta é Yesdado M = 2 resposta é Yesdado M = 4 resposta é No

O próximo slide mostra o grafo de MEF

5

Count = 0Index = 0

rese

t = 1

BVector(Index) =

1

BVector(Index) = 0

Count ++Index ++

Index ++Count=0

Result: Yes

count=M

countMandIndex=N

Result: No

countM and IndexN

and BVector(Index) = 1

countM and IndexN

and BVector(Index) = 0 Index=N

BVector(Index) = 1and Index N


BVector(Index) = 1 - X1BVector(Index) = 0 - not X1count=M - X2countM - not x2Index=N-1 - X3Index N-1 - not X3

a0 a1

a2

a3

a4y1: Count=0;y2: Index=0;y3: Count++;y4: Index++;y5=1: Yesy5=0: No

A={ao,…,a4};X={X1,X2,X3};Y={y1,…,y5}.

6

Count = 0Index = 0 y1, y2

rese

t = 1

X1

not X1

Count ++Index ++ y3, y4

Index ++Count=0 y1, y4

Result: Yes y5

X2

not X2andX3

Result: No

not X2 and not X3

and X1

no

t X

2 an

d n

ot

X3

and

n

ot

X1

X3

X1not X3

not X1not X3

BVector

No or Yes

Count

Index

FSM

y1: Count=0;y2: Index=0;y3: Count++;y4: Index++;y5=1: Yesy5=0: No

a0

a1

a2

a3

a4

a1

a3X21

else

X31 a4

else

X11 a1

a2

7

Count = 0Index = 0 y1, y2

rese

t = 1

X1

not X1


Index ++Count=0 y1, y4

Result: Yes y5

X2

not X2andX3

Result: No

not X2 and not X3

and X1

not X2 and not X3and not X1

X3

X1not X3

not X1not X3

BVector

No or Yes

Count

Index

FSM

y1: Count=0;y2: Index=0;y3: Count++;y4: Index++;y5=1: Yesy5=0: No

a0

a1

a2

a3

a4

8

Count = 0Index = 0

rese

t = 1

BVector(Index) =

1

BVector(Index) = 0

Count ++Index ++

Index ++Count=0

Result: Yes

count=McountMand

Index=N

Result: No

countM and IndexN

and BVector(Index) = 1

countM andIndexN and BVector(Index) = 0

Index=N




a0 a1

a2

a3

a4

a1

a3X21

else

X31 a4

else

X11 a1

a2

9

case FSMstate is when a0 => Count <= 0; Index <= 0;

if BVector(0) = '1' then FSMnext_state <= a1;else FSMnext_state <= a2;

end if; when a1 => Count <= Count + 1; Index <= Index + 1; if (Count = NumberOfSucOnes-1)then FSMnext_state <= a3;

elsif (Index = SizeOfVector-1) then FSMnext_state <= a4;elsif (BVector(index+1) = '1') then FSMnext_state <= a1;else FSMnext_state <= a2;

end if;

a1

a3X

21

els

e X3

1a4

els

e X1

1a1

a2



a1

10

MEF

11

entity FSM_succeeding_ones is generic (AddressBits : natural; StateMaxValue : natural; NumberOfColumns : natural; SizeOfVector : natural; NumberOfSucOnes : natural ); Port ( ASCII_in : in STD_LOGIC_VECTOR (7 downto 0); ASCII_out : out STD_LOGIC_VECTOR (7 downto 0); Address_in : in STD_LOGIC_VECTOR (AddressBits - 1 downto 0); Address_out : out STD_LOGIC_VECTOR (AddressBits - 1 downto 0); clk : in STD_LOGIC; rst : in STD_LOGIC; WE_in : in STD_LOGIC; WE_out : out STD_LOGIC);end FSM_succeeding_ones;

architecture Behavioral of FSM_succeeding_ones is

signal BVector : STD_LOGIC_VECTOR(SizeOfVector-1 downto 0); -- Binary Vectorsignal state : integer range 0 to StateMaxValue;signal line, line_local : integer range 0 to 39;signal column, column_local : integer range 0 to 79;signal ASCII_local : std_logic_vector(7 downto 0);signal ASCII_state : std_logic_vector(7 downto 0);signal YesNo: string(1 to 5) := " ";signal BVectorName: string(1 to 26) := "Given binary vector = ";constant TextOutBegin: string(1 to 11) := "Contains ";constant TextOutEnd: string(1 to 19) := " succeeding ones: ";signal count : integer range 0 to NumberOfSucOnes;signal index : integer range 0 to SizeOfVector;

type state_type is (a0,a1,a2,a3,a4); signal FSMstate, FSMnext_state : state_type;

beginBVector(conv_integer(Address_in(3 downto 0))) <= '0' when rst = '1' else

ASCII_in(0) when ((ASCII_in >= "00110000") or (ASCII_in <= "00110001")) and (WE_in = '1');

-------------- FSM begin

0101110101101011

BVector

No or Yes

Count

Index

FSM

A={ao,…,a4};

12

BVector(conv_integer(Address_in(3 downto 0))) <= '0‘when rst = '1' else

ASCII_in(0)when ((ASCII_in >= "00110000") or

(ASCII_in <= "00110001"))and (WE_in = '1');

do teclado ou 0 ou 1

indice 0

13

-------------- FSM begin

process(clk,rst)begin

if rst = '1' thenFSMstate <= a0;

elsif rising_edge(clk) thenFSMstate <= FSMnext_state;

end if;end process;

process(clk,rst)begin if rst = '1' then YesNo <= " ";

elsif falling_edge(clk) then case FSMstate is

when a0 => Count <= 0; Index <= 0;if BVector(0) = '1' then FSMnext_state <= a1;

else FSMnext_state <= a2;end if;

Count = 0Index = 0

Count ++Index ++

a1

a2

rese

t = 1

Index ++Count=0

a0BVector(In

dex) = 1

BVector(Index) = 0

0

0

14

when a1 => Count <= Count + 1; Index <= Index + 1;if (Count = NumberOfSucOnes-1)then FSMnext_state <= a3; elsif (Index = SizeOfVector-1) then FSMnext_state <= a4; elsif (BVector(index+1) = '1') then FSMnext_state <= a1; else FSMnext_state <= a2;end if;

when a2 => Count <= 0; Index <= Index + 1;if (Index = SizeOfVector-1) then FSMnext_state <= a4; elsif (BVector(index+1) = '0') then FSMnext_state <= a2; else FSMnext_state <= a1;end if;

when a3 => YesNo <= " Yes "; FSMnext_state <= a0;when a4 => YesNo <= " No "; FSMnext_state <= a0;when others => null;

end case; else null; end if;end process;

-------------- FSM end

signal YesNo: string(1 to 5) := " ";

15

process(clk, rst)begin if rst = '1' then state <= 0; elsif falling_edge(clk) then I f state=StateMaxValue then state<=0; else state<= state + 1; end if; end if;end process;process(clk, rst)begin if rst= '1' then null; elsif rising_edge(clk) then case state is

when 1 to 26 => line_local <= 9; column_local <= 14 + state;ASCII_local <= std_logic_vector(to_unsigned(character'pos(BVectorName(state)), 8));

when 27 to 42 => line_local <= 9; column_local <= 14 + state;ASCII_local <= "0011000" & BVector(state-27);

when 43 to 53 => line_local <= 10; column_local <= 14 + state - 42;ASCII_local <= std_logic_vector(to_unsigned(character'pos(TextOutBegin(state-42)), 8));

when 54 => line_local <= 10; column_local <= 14 + 11 + 1;ASCII_local <= "0011" & conv_std_logic_vector(NumberOfSucOnes,4);

when 55 to 73 => line_local <= 10; column_local <= 14 + 11 + 1 + state - 54;ASCII_local <= std_logic_vector(to_unsigned(character'pos(TextOutEnd(state-54)), 8));

when 74 to 78 => line_local <= 10; column_local <= 14 + 11 + 1 + state - 54;ASCII_local <= std_logic_vector(to_unsigned(character'pos(YesNo(state-73)), 8));

when others => null; end case; end if;end process;

WE_out <= '1';ASCII_out <= ASCII_local;column <= column_local;line <= line_local;Address_out <= conv_std_logic_vector((line*NumberOfColumns + column),AddressBits);

end Behavioral;

16

Given binary vector = 1010101101111101Contains 5 succeeding ones: Yes

Given binary vector = 1010101101011101Contains 5 succeeding ones: No

1. 2 memória (r-bit register) circuito combinatório d1d1 drdr trtr t1t1 x1x1 xlxl y1y1 ynyn...

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